Timing Controller Clock Training Patterns for Faster Signal Locking
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Solution Overview
Problem
Existing display devices face issues with Inter-Symbol Interference (ISI) jitter and noise concentration phenomena due to regular repetitive clock training patterns, which affect the clock signal's frequency and phase recovery.
Innovation Solution
A timing controller that provides various clock training patterns with sub-patterns, including sub-pattern period and initial-level period setting values, to improve clock signal locking time by anticipating transition points and reducing ISI jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a regular repetitive clock training pattern is used, then the clock signal can be recovered periodically, but ISI jitter and noise concentration occur
Solution Approach 1:
The patent applies dynamics by making the clock training pattern variable rather than static. The timing controller dynamically changes the training pattern based on configuration information, switching between different patterns (e.g., 2T, 4T, 8T patterns with different transition densities) to adapt to different recovery conditions, thereby preventing ISI jitter and noise concentration while maintaining reliable clock signal recovery
Solution Approach 2:
The patent changes parameters of the clock training pattern including transition density, pattern period, and configuration information. By varying these parameters according to different recovery stages and conditions, the system optimizes clock signal recovery performance while minimizing harmful effects like ISI jitter and noise concentration
2Object-affected harmful factors
If various clock training patterns are transmitted with configuration information, then ISI jitter and noise concentration are reduced, but the system complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-defining multiple clock training patterns and their configuration information in the timing controller. These patterns and configurations are prepared in advance and selected based on recovery conditions, which simplifies the real-time decision-making process and reduces system complexity despite having multiple patterns available
Solution Approach 2:
The patent achieves universality by designing a multi-functional clock training mechanism that can handle different recovery scenarios with a single integrated system. The same timing controller and CDR circuit handle both simple and complex training patterns, and the configuration information format is standardized to accommodate various pattern types, reducing overall system complexity
3Loss of time
If configuration information on various clock training patterns is provided in advance, then the locking time of clock signal is decreased, but the data transmission overhead increases
Solution Approach 1:
The patent applies preliminary action by providing configuration information for clock training patterns in advance, during the initial setup or before actual data transmission begins. This allows the CDR circuit to be pre-configured with the appropriate training pattern parameters, enabling faster locking without requiring extensive configuration data to be transmitted during operation
Solution Approach 2:
The patent extracts the configuration information for clock training patterns from the main data stream and provides it through separate control channels or pre-configuration mechanisms. This separation removes the overhead of transmitting configuration data with every data packet, reducing information loss while maintaining fast locking capability
Data Source
AI summary
A display device including: pixels connected to data lines; a data driver configured to provide data voltages to the data lines; and a timing controller connected to the data driver through a clock training line and a clock data line, wherein the timing controller provides a clock training pattern to the clock data line when the timing controller provides a clock training signal having a first logic level to the clock training line, and provides a clock data signal to the clock data line when the timing controller provides the clock training signal having a second logic level to the clock training line, and wherein the timing controller provides a first configuration signal for a next clock training pattern when the clock training signal having the second logic level is provided to the clock training line.