Timing Controller Clock Signal Segmentation for Touch Noise Reduction
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Solution Overview
Problem
In display apparatuses, the coupling noise generated by clock signals on touch structure layers can reach significant levels, leading to falsely reported touch points and reduced product yield due to the overlap of signal lines and touch structures, especially with black matrices contributing to increased capacitance.
Innovation Solution
A timing controller (TCON) with a field programmable gate array (FPGA) generates clock signals with specific sub-signal periods and phases, ensuring the clock signal is in a toggle state throughout the image frame, reducing coupling noise by outputting different sub-signals during display and non-display stages, and maintaining a continuous signal with equal periods to minimize noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If clock signal lines are routed under the touch structure layer to save space, then device integration is improved, but coupling noise increases due to capacitance between signal lines and touch structures
Solution Approach 1:
The clock signal is divided into two sub-signals (first clock sub-signal and second clock sub-signal) with different periods. The first sub-signal is output during the display stage and the second sub-signal is output during the non-display stage. This segmentation allows the clock signal to be optimized for different operational phases, reducing coupling noise with the touch structure layer while maintaining proper gate drive functionality.
Solution Approach 2:
The patent changes the temporal parameters of the clock signal by outputting different sub-signals with different periods during different stages (display vs. non-display). This parameter change reduces the coupling capacitance effect on the touch structure layer during critical periods while maintaining signal integrity for gate drive operations.
2Productivity
If clock signal frequency is increased to improve scanning speed, then productivity is improved, but coupling noise increases affecting touch accuracy
Solution Approach 1:
The patent employs periodic action by outputting different clock sub-signals with different periods during display and non-display stages. During the display stage, a first period is used to maintain scanning speed, while during the non-display stage, a second period is used to reduce coupling noise. This periodic variation in signal frequency resolves the contradiction between maintaining high scanning speed and reducing touch detection interference.
3Ease of operation
If continuous clock signal is provided to gate drive circuit, then device operation is simplified, but noise interference increases on touch structure layer
Solution Approach 1:
The continuous clock signal is segmented into distinct first and second clock sub-signals corresponding to display and non-display stages. This segmentation allows the system to maintain continuous operation (ease of operation) while reducing noise interference during the non-display stage by providing a different clock sub-signal with optimized parameters that minimize coupling with the touch structure layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces coupling noise at the touch structure layer, minimizing falsely reported points and improving the yield of display apparatuses by maintaining consistent input charges during both display and non-display stages, thus enhancing touch accuracy.
Implementation Method 1
the coupling noise generated by clock signals on touch structure layers can reach significant levels... due to the overlap of signal lines and touch structures, especially with black matrices contributing to increased capacitance
Data Source
AI summary
A timing controller includes: a field programmable gate array configured to generate a reference clock signal, and obtain at least one group of clock signals according to the reference clock signal. Each group of clock signals includes at least two clock signals, and a waveform of each clock signal is same as a waveform of the reference clock signal, and active levels in different clock signals are provided with a delay of a preset duration. The reference clock signal includes a first clock sub-signal for first duration and a second clock sub-signal for a second duration. At least one output interface group is connected to the field programmable gate array. Each output interface group includes at least two output interfaces, and each of the at least two output interfaces is configured to output one clock signal of a group of clock signals corresponding to the output interface group.