Display Timing Controller With Dedicated Communication Processing
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Solution Overview
Problem
The existing polling and interrupt schemes in timing controllers for display devices cause processor and system bus overload, leading to delays in operating time due to frequent state checks and interrupt determinations.
Innovation Solution
A timing controller with a dedicated processor that stores and interprets communication-dedicated instructions, sequentially transmits request signals, and receives completion signals, reducing the need for continuous state checks and interrupt determinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polling scheme is used to check the state of the dedicated module, then the system can monitor the module state, but the processor and system bus become overloaded
Solution Approach 1:
The patent introduces a dedicated processor as an intermediary between the general processor and the dedicated module. The dedicated processor handles communication with the dedicated module, including checking operation completion, while the general processor focuses on generating communication control signals. This division reduces the burden on the general processor and system bus, resolving the overload issue while maintaining reliable monitoring.
2Device complexity
If an interrupt scheme is used to check the module state, then the processor overload is reduced, but a delay in operating time occurs due to interrupt determination
Solution Approach 1:
The dedicated processor autonomously checks the operation completion of the dedicated module and manages communication timing without requiring interrupt intervention from the general processor. The general processor simply issues communication control signals, while the dedicated processor independently handles the timing-critical operations, eliminating interrupt determination delays while keeping the general processor lightly loaded.
3Loss of information
If the general processor checks operation completion in a polling scheme, then communication status can be confirmed, but the processor and system bus experience overload
Solution Approach 1:
The patent segments the processor functions into a general processor for high-level control signal generation and a dedicated processor for communication status monitoring and timing management. This segmentation allows the general processor to avoid the overhead of frequent polling, while the dedicated processor efficiently handles communication status confirmation, thereby improving overall system productivity without sacrificing status information accuracy.
Data Source
AI summary
A timing controller suitable for providing image data and control signals to a display panel includes at least one dedicated controller configured to instruct the display panel to perform a specific operation; and a dedicated processor configured to store at least one communication-dedicated instruction, interpret, according to a communication signal designating an operation area of a communication-dedicated instruction received from an external or internal general processor, the communication-dedicated instruction within the operation area, sequentially transmit communication request signals to the corresponding dedicated controller, sequentially receive communication completion signals from the dedicated controller, and transmit an operation completion signal to the general processor when a communication completion signal for the communication-dedicated instruction of the operation area is finally received.