Timing Controller Data Segmentation for EMI Reduction
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Solution Overview
Problem
Liquid crystal displays face challenges in achieving high resolution due to excessive electromagnetic interference (EMI) and noise generation, particularly when using high-speed data transmission frequencies required for mobile displays.
Innovation Solution
A display device that reduces data transmission frequency by using a timing controller with a clock conversion unit to generate low-speed clock signals, a data division unit to split display data into multiple streams, and an average picture level/pixel processing algorithm unit to adjust and transmit data synchronized with these low-speed clock signals, thereby minimizing EMI and noise while maintaining high-speed data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed clock signals are used to transmit display data at high resolution, then data transmission speed is improved, but electromagnetic interference and noise are excessively generated
Solution Approach 1:
The patent divides display data into multiple data lanes (e.g., 4 lanes for WVGA resolution) and transmits them using multiple low-speed clock signals instead of a single high-speed clock signal. This segmentation approach maintains high data transmission capacity while reducing the frequency of individual clock signals from 25 MHz to lower frequencies, thereby minimizing electromagnetic interference and noise generation.
2Manufacturing precision
If high-speed clock signals are used to achieve high resolution, then data transmission capability is improved, but the clock frequency exceeds the rated range of the mobile industry processor interface
Solution Approach 1:
The patent segments display data into multiple parallel data streams, each transmitted at a reduced clock frequency within the MIPI rated range (12.3-20 MHz). For example, WVGA resolution data is divided into 4 lanes transmitted at lower frequencies, achieving high resolution output while keeping individual clock frequencies within acceptable limits.
Solution Approach 2:
The patent transitions from a single high-frequency clock dimension to multiple lower-frequency clock dimensions (multiple data lanes). This dimensional change allows the system to achieve the same data throughput through parallel transmission at reduced frequencies, compatible with MIPI interface specifications.
3Object-generated harmful factors
If multiple low-speed clock signals are used to transmit data, then electromagnetic interference is reduced, but the system complexity increases due to multiple data ports and clock conversion
Solution Approach 1:
The timing controller is designed with multi-functionality to perform clock conversion, data division, color space conversion, and APL/PPA processing within a single integrated unit. This universal design consolidates multiple functions that would otherwise require separate components, reducing overall system complexity despite using multiple low-speed clock signals for data transmission.
Data Source
AI summary
Disclosed is a display device that reduces a data transmission frequency, thereby minimizing generation of EMI noise and realizing high resolution. The display device includes a display panel to display images, a gate driver to drive gate lines of the display panel, a data driver to drive data lines of the display panel, a timing controller to control the gate driver and the data driver and to arrange and supply display data to the data driver, and N (N is a natural number greater than 1) data ports to transmit the display data while being synchronized with N low-speed clock signals having a lower frequency than a clock signal necessary to transmit the display data in the timing controller.