Timing Controller Phase Adjustment for Multi-Drop Display Skew

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Solution Overview

Problem

In multi-drop architectures, the clock and frame signal transmission paths exhibit different delays, leading to varying timing skews for source drivers, causing some drivers to incorrectly latch data due to mismatched phase relationships.

Innovation Solution

A timing controller adjusts the phase of the clock and frame signals to compensate for different transmission path delays, ensuring each source driver receives signals with optimized timing skews.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a multi-drop architecture is used with a common transmission path for clock and frame signals, then device complexity is reduced and ease of manufacture is improved, but transmission path delays differ between clock and frame signals causing timing skew variations across source drivers

Engineering Contradiction:
Improvetransmission path structureVSAvoidtiming skew accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The frame signal transmission path is segmented into multiple independent paths, each corresponding to a different source driver. Each path can have its own phase adjustment mechanism, allowing independent timing calibration for each segment while still using the common multi-drop architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Phase adjustment capabilities are distributed locally to different segments of the transmission path. Each source driver receives frame signals through a dedicated path with locally adjustable phase characteristics, enabling precise timing compensation without affecting other segments.

Inventive Principle:
Principle #3Local quality

2Device complexity

If the clock signal and frame signal are transmitted through the same transmission path, then the architecture is simplified, but the timing skew between clock and frame signals varies for different source drivers causing data latching errors

Engineering Contradiction:
Improvesignal transmission architectureVSAvoiddata latching accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The frame signal path is divided into separate segments for different source drivers, with each segment having independent phase control. This segmentation allows the clock signal to remain common while frame signal timing can be independently adjusted for each driver.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The phase relationship between clock and frame signals is made dynamically adjustable for each source driver. Phase shifters or delay elements are incorporated into each frame signal path to dynamically compensate for timing variations and ensure accurate data latching.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If different source drivers receive clock and frame signals with different timing skews, then transmission path differences are reflected, but some source drivers cannot correctly latch data due to phase mismatch

Engineering Contradiction:
Improvetransmission path delay variationVSAvoiddata latching precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Each source driver is equipped with or assigned a dedicated phase adjustment mechanism that locally compensates for its specific timing skew. This local quality approach ensures that each driver receives optimally timed signals despite variations in transmission path delays.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The phase parameter of the frame signal is independently adjusted for each source driver to compensate for timing skew variations. By changing the phase parameter locally at each receiver, accurate data latching is achieved despite different transmission path characteristics.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12555513B1Timing controller and operation method thereof
Publication Date: 2026.02.17 NOVATEK MICROELECTRONICS CORP
  • US12555513B1 patent drawing
  • US12555513B1 patent drawing
  • US12555513B1 patent drawing

AI summary

A timing controller and an operation method of the timing controller are provided. The timing controller includes a timing signal generation part and a frame signal generation part. The timing signal generation part generates a clock signal to a plurality of source drivers for driving a display panel. The frame signal generation part generates a frame signal synchronized with the clock signal. The frame signal includes a plurality of data segments corresponding to different source drivers. The timing controller adjusts a phase of at least one of the clock signal and the frame signal, so that the clock signal has different timing skews for different data segments and is adapted to different transmission path delays between the timing controller and the source drivers.