Timing Controller Self-Test Using Clock Edge Counting
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Solution Overview
Problem
Conventional liquid crystal display panels face issues with the inability to check the normal operation of the timing controller before packaging, leading to defective chips being manufactured, and the need to identify abnormal timing controllers to reduce packaging costs.
Innovation Solution
A timing controller that generates a clock signal using an external first clock, creates a test pulse, and latches it to generate test clocks, determining normal operation by counting rising and falling edges, allowing identification of abnormal controllers before packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the timing controller and memory are packaged together as MCP before operation checking, then the packaging process is completed, but the IP operation cannot be verified and defective chips are produced
Solution Approach 1:
The patent applies preliminary action by performing IP operation verification through test pulse generation and edge counting before the MCP packaging process. The timing controller generates test pulses and counts rising/falling edges to verify IP functionality in advance, ensuring that only normally operating IPs are packaged, thus preventing defective chips while maintaining packaging productivity
Solution Approach 2:
The patent implements feedback by using the counted number of rising and falling edges from test pulses to determine IP operation status. This feedback mechanism provides verification results that guide the packaging decision process, ensuring that only IPs with normal operation (matching expected edge counts) are packaged together with memory
2Ease of manufacture
If the timing controller IP is abnormal but still packaged, then the packaging process is completed, but packaging cost increases due to defective chips
Solution Approach 1:
The patent performs preliminary IP operation verification by generating test pulses and counting edges before packaging. This advance checking identifies abnormal IPs that would otherwise be packaged defectively, preventing waste of packaging resources and reducing packaging costs while maintaining ease of manufacture for normally operating IPs
3Measurement precision
If the timing controller generates and tests clock signals with multiple edges, then the operation verification is achieved, but the device complexity increases
Solution Approach 1:
The patent applies self-service by having the timing controller generate its own test pulses and perform its own IP operation verification internally. The controller uses its existing clock generation and counting capabilities to self-test, avoiding the need for external complex test equipment while achieving accurate operation verification through edge counting
Data Source
AI summary
A timing controller generates a second clock by using a first clock, generates a test pulse by using the second clock, and generates a plurality of test clocks by latching the test pulse. The timing controller determines whether the clock signal is normally generated, by using the number of a plurality of rising edges included in a cycle of the test pulse and the number of a plurality of falling edges included in the cycle of the test pulse. The plurality of rising edges are rising edges of the plurality of test clocks, and the plurality of falling edges are falling edges of the plurality of test clocks.