Timing Controller Enable Signal Synchronization for Flat Panel Displays
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Solution Overview
Problem
In flat panel display devices with half source driving (HSD) structure, the delay of output enable signal causes different turned-on times for gate driver ICs, leading to wrongly charged signals and sloped voltage differences, resulting in line mura and color unevenness in displayed images.
Innovation Solution
A control method for the output signal that adjusts the timing of enable signals for gate drivers by providing a first enable signal after a shorter time length and a second enable signal after a longer time length, compensating for the difference in transmission times across different gate drivers to synchronize the arrival times of enable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the output enable signal transmission path is used in wire on array manner, then the gate driver ICs can be integrated with the display panel, but the signal transmission delay causes different turned-on times for different gate driver ICs, resulting in sloped voltage differences and color unevenness
Solution Approach 1:
The patent applies preliminary action by adjusting the timing of output enable signals before they reach different gate driver ICs. Specifically, the timing controller provides the output enable signal to different gate driver ICs at different times based on their respective signal transmission delays, ensuring that all gate driver ICs are turned on simultaneously despite the varying transmission path lengths.
2Manufacturing precision
If the period of logic low level of the output enable signal is lengthened to compensate for transmission delay, then the turned-on time difference between gate driver ICs is reduced, but the gate enable time becomes excessively short, resulting in insufficient charging time for display data signals
Solution Approach 1:
The patent applies local quality by providing different timing adjustments to different gate driver ICs based on their specific transmission path characteristics. Instead of uniformly lengthening the enable signal period for all ICs, the timing controller individually adjusts the output enable signal timing for each gate driver IC according to its distance and signal transmission delay from the timing controller, thereby maintaining adequate gate enable time while achieving synchronization.
3Manufacturing precision
If different time lengths are used for different parts of pulses, then the arrival times of enable signals at different gate drivers are synchronized, but the control logic becomes more complex
Solution Approach 1:
The patent implements feedback by pre-calculating and storing the optimal output enable signal timing for each gate driver IC based on their transmission path characteristics. The timing controller uses this pre-stored timing information to automatically adjust the enable signal timing, eliminating the need for complex real-time calculations and simplifying the control logic while achieving precise synchronization.
Data Source
AI summary
An exemplary control method of an output signal (e.g., from a timing controller in a flat panel display device) is adapted to be operative with a first signal with multiple pulses. In the control method, during a first time segment including part of the pulses of the first signal, a first enable signal is provided passing through a transmission path after a first time length from a rising edge of each of the part of the pulses. During a second time segment including another part of the pulses of the first signal, a second enable signal is provided passing through a part of the transmission path after a second time length from a rising edge of each of the another part of the pulses. The first time length is shorter than the second time length.