Timing Controller Reset Circuit for GOE Signal Stabilization
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Solution Overview
Problem
Liquid crystal display devices face issues with electromagnetic interference and external noise due to high-frequency data and clock signals, leading to abnormal image display and restricted data transmission bits, which are not adequately addressed by existing LVDS technology.
Innovation Solution
A reset circuit and filtering circuit are introduced in the timing controller, comprising a transistor, resistors, and a capacitor, to stabilize the GOE signal duration and eliminate clock signal impulses, ensuring normal operation of the gate and source drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LVDS receiving units convert LVDS to TTL signals in the timing controller, then data transmission speed is improved, but voltage induction from LVDS causes the GOE signal duration to be shortened below the required 16 msec threshold
Solution Approach 1:
A filtering circuit is introduced as an intermediary component between the LVDS receiving unit and the gate driver. This filtering circuit includes a capacitor connected to the GOE signal line, which acts as a mediator to store and release electrical charge, thereby extending the GOE signal duration to meet the 16 msec requirement while preserving the high-speed LVDS data transmission capability.
Solution Approach 2:
The filtering circuit with capacitor is designed to anticipate and compensate for the voltage induction effect before it causes malfunction. By pre-charging the capacitor during the LVDS signal transition, the circuit ensures that the GOE signal maintains sufficient duration even when voltage induction occurs, preventing gate driver malfunction before it can happen.
2Manufacturing precision
If high-frequency TTL signals are used for data and clock transmission, then display resolution is improved, but electromagnetic interference and external noise increase causing abnormal image display
Solution Approach 1:
The patent converts the harmful voltage induction effect into a beneficial extension of the GOE signal duration. By strategically placing a capacitor in the filtering circuit, the voltage induction that would normally cause malfunction is instead utilized to charge the capacitor, which then releases charge to extend the GOE signal duration, transforming a harmful effect into a useful function.
Solution Approach 2:
The filtering circuit serves as an intermediary that isolates the high-frequency LVDS signals from sensitive control signal lines. The capacitor in the filtering circuit acts as a mediator that filters out high-frequency noise and voltage induction effects, allowing high-resolution display through LVDS while protecting the gate driver from electromagnetic interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures a reliable liquid crystal display device with extended GOE signal duration and reduced clock signal impulses, enhancing display quality and reducing image interference.
Implementation Method 1
a capacitor including a first electrode connected to the fifth node and a second electrode grounded
Implementation Method 2
a transistor including an emitter connected to a first node, a base connected to a second node and a collector connected to a third node
Data Source
AI summary
A reset circuit of a timing controller includes: a transistor including an emitter connected to a first node, a base connected to a second node and a collector connected to a third node, a digital input voltage (DVCC) being applied to the first node; a first resistor connected between the first and second nodes; a second resistor connected between the second node and a fourth node, the fourth node being grounded; a third resistor connected between the third and fourth nodes; a fourth resistor connected between the third node and a fifth node, the fifth node being connected to an input terminal of the timing controller; and a capacitor including a first electrode connected to the fifth node and a second electrode grounded.