Timing Controller Line Buffer Memory Cell Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing data access methods for timing controllers in flat panel displays are inefficient in utilizing memory cells, as each memory cell is used only once, leading to high memory costs for displaying images.
Innovation Solution
A data access method that divides the line buffer's memory cells into two sections, where the first section has more cells than the second, allowing for writing and reading pixel data in a specific order to optimize memory usage, thereby reducing the overall number of memory cells required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If each memory cell is used only once for writing and reading pixel data, then the data access is simple, but the memory cell utilization efficiency is low and memory cost is high
Solution Approach 1:
The line buffer memory cells are divided into a first section and a second section. The first section stores pixel data for current display, while the second section stores pixel data for subsequent display. This segmentation allows different sections to be accessed differently, enabling memory cells to be reused after reading, thereby improving utilization efficiency without complicating the overall access mechanism
Solution Approach 2:
Memory cells in the second section serve dual purposes: they store pixel data for subsequent display rows and can be reused for storing pixel data of current display rows after the subsequent row data is written. This multi-functionality allows the same memory cells to be accessed multiple times, improving efficiency while maintaining simple access patterns
2Reliability
If more memory cells are allocated for line buffer, then pixel data can be stored for dual-port output, but memory cost increases
Solution Approach 1:
The patent implements dynamic data packing where pixel data from different memory sections is selectively combined based on display requirements. The controller dynamically determines which data to read from the first section and which from the second section, allowing flexible use of available memory cells to meet dual-port output requirements without allocating excessive memory resources
Solution Approach 2:
The patent changes the organization parameter of memory cell allocation by dividing cells into two sections with different access patterns. This parameter change enables the same physical memory cells to serve multiple functions, reducing the total quantity needed while maintaining the reliability of pixel data storage for dual-port operation
Data Source
AI summary
A data access method for a timing controller of a flat panel display includes forming a line buffer including a plurality of memory cells in the timing controller, dividing the plurality of memory cells into a first section and a second section, wherein the number of memory cells in the first section is greater than the number of memory cells in the second section, writing a first number of pixel data into the first section, wherein the first number of pixel data is included in a plurality of pixel data corresponding to a row of a frame, writing a second number of pixel data into the second section, wherein the second number of pixel data is included in the plurality of pixel data, and the first number is equal to the second number, and reading the plurality of pixel data from the plurality of memory cells according to an order.