Timing Controller for Pixel Level Multiplexing Display Panels
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Solution Overview
Problem
Conventional timing controllers are not applicable for pixel level multiplexing display panels as they require changes to the architectures of scan and data driving circuits, limiting circuit design flexibility and increasing manufacturing costs.
Innovation Solution
A timing controller with a memory and memory controller, utilizing odd-field and even-field memory blocks, and a scan control signal generator to manage gate output enable signals, allowing data transfer and storage without altering the conventional scan and data driving circuits, enabling efficient control of pixel level multiplexing display panels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional timing controller is used for pixel level multiplexing display panel, then manufacturing cost increases and circuit design flexibility decreases, but if the architecture of scan and data driving circuits is changed, then the timing controller becomes applicable
Solution Approach 1:
The memory is divided into separate odd-field memory blocks and even-field memory blocks, allowing independent storage and control of data for different pixel groups. This segmentation enables the timing controller to manage pixel level multiplexing without requiring changes to the scan and data driving circuit architectures.
Solution Approach 2:
The timing controller acts as an intermediary between the data source and the display panel, implementing the pixel level multiplexing logic within itself. By using memory blocks and control logic to buffer and selectively output data, the timing controller mediates the data flow to match the multiplexed panel requirements without modifying external driving circuits.
2Ease of manufacture
If the architecture of scan and data driving circuits is changed to make timing controller applicable, then manufacturing cost increases, but if conventional architecture is maintained, then timing controller cannot control pixel level multiplexing display panel
Solution Approach 1:
The timing controller is designed with universal functionality to handle both conventional display panels and pixel level multiplexing display panels. By incorporating configurable memory blocks and flexible control logic that can operate in different modes, the timing controller achieves multi-functionality without requiring different hardware architectures for different panel types.
Solution Approach 2:
The timing controller changes operational parameters such as memory block selection, data output timing, and control signal generation to adapt to pixel level multiplexing requirements. By adjusting these parameters rather than changing the physical architecture, the controller maintains manufacturing simplicity while achieving the required adaptability.
Data Source
AI summary
A timing controller including a memory and a memory controller is provided. The memory includes an odd-field block and an even-field block. The memory controller is coupled to the memory and controls the memory. When two of a first, a second and a third gate output enable signals output by the timing controller are active, the memory is controlled to output the data of the (I−1)th scan line stored in the odd-field block. When one of the first, the second and the third gate output enable signals output by the timing controller is active, and the other two signals are inactive, the memory is controlled to output the data of Jth scan line stored in the even-field block and write an odd-field field data of the (J+1)th scan line to the odd-field block and write an even-field field data of the (J+1)th scan line to the even-field block.