Timing Controller Pin Reduction via Selecting Module
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Solution Overview
Problem
Conventional gate driver on array (GOA) driving circuits face inefficiencies due to the inability of timing controllers to provide an adequate number of pins to satisfy the requirements of level shifters, leading to wasteful pin usage.
Innovation Solution
A driving circuit design that includes a timing controller, a selecting module with switch transistors, and a control unit, which allows for the efficient distribution of clock signals from the timing controller to multiple input pins of the level shifter through the use of MOSFET switch transistors, enabling the reuse of timing controller pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a timing controller directly connects to a level shifter with multiple input pins, then the level shifter can receive clock signals, but the timing controller requires an equal or greater number of pins which leads to pin wastage
Solution Approach 1:
The patent divides the connection between timing controller and level shifter into multiple selecting units (first selecting unit, second selecting unit, etc.). Each selecting unit contains switch transistors that can selectively connect different pins of the timing controller to different input pins of the level shifter. This segmentation allows one timing controller pin to serve multiple level shifter input pins through time-multiplexed switching, thereby reducing the total number of pins required on the timing controller.
2Reliability
If the timing controller provides enough pins for all level shifter inputs, then all input pins can be satisfied, but the timing controller pins are used wastefully
Solution Approach 1:
The patent employs periodic switching of the selecting units to sequentially connect different timing controller pins to different level shifter input pins. The control unit alternates the on/off states of switch transistors in different selecting units at different time periods, enabling one timing controller pin to serve multiple level shifter inputs over time. This periodic action ensures reliable signal transmission to all level shifter inputs while significantly improving pin usage efficiency on the timing controller.
3Quantity of substance
If switch transistors are added to create selecting units, then pin efficiency improves, but the circuit complexity increases
Solution Approach 1:
The patent designs the selecting units with switch transistors that can be controlled by a universal control unit to perform multiple functions. The same selecting unit structure and control mechanism can sequentially connect different timing controller pins to different level shifter input pins, making the circuit elements multi-functional. This universality allows the circuit to achieve high pin efficiency while managing complexity through reusable, standardized components rather than requiring unique complex connections for each pin pair.
Data Source
AI summary
A driving circuit that includes a timing controller, a selecting module connected to the timing controller, and a level shifter connected to the selecting module, wherein the timing controller includes N pins, each of the pins provides a clock signal, and N is a positive integer; the selecting module includes N selecting units, an input terminal of each of the selecting units is connected to a corresponding pin of the timing controller, output terminals of each of the selecting units are connected to M input pins of the level shifter, and M is greater than or equal to 2. The driving circuit according to the present invention individually passes clock signals of a timing controller through selecting units and outputs to a level shifter, and pins of the timing controller can be substantially saved.