Timing Controller Pixel Clock Frequency Adjustment
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Solution Overview
Problem
As image data resolution increases, the frequency of the pixel clock also increases, leading to higher power consumption in the image processing circuit and potential noise interference with wireless communication.
Innovation Solution
A timing controller that includes a line memory, frequency synthesizer, and image processing circuit, allowing for the generation of an internal pixel clock with a frequency adjusted by a coefficient K, which can be less than or greater than 1, to reduce power consumption and noise interference by adjusting the pixel number of the horizontal blank duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pixel clock frequency is increased to handle higher resolution image data, then the image processing capability is improved, but the power consumption of the image processing circuit increases
Solution Approach 1:
The patent applies dynamics by making the pixel clock frequency adjustable rather than fixed. The timing controller can dynamically change the pixel clock frequency based on the actual image processing requirements and workload, allowing the system to operate at lower frequencies when possible to reduce power consumption while maintaining the capability to operate at higher frequencies when handling high-resolution data
Solution Approach 2:
The patent changes the frequency parameter of the pixel clock from a fixed high value to a variable parameter that can be adjusted according to actual needs. By modifying the frequency parameter dynamically, the system achieves lower power consumption during normal operation while retaining the ability to process high-resolution data when required
2Productivity
If the pixel clock frequency is increased to handle higher resolution image data, then the image processing capability is improved, but noise interference with wireless communication increases
Solution Approach 1:
The patent applies dynamics by making the pixel clock frequency adjustable rather than fixed. The timing controller can dynamically change the pixel clock frequency based on the actual image processing requirements and workload, allowing the system to operate at lower frequencies when possible to reduce power consumption while maintaining the capability to operate at higher frequencies when handling high-resolution data
Solution Approach 2:
The patent changes the frequency parameter of the pixel clock from a fixed high value to a variable parameter that can be adjusted according to actual needs. By modifying the frequency parameter dynamically, the system achieves lower power consumption during normal operation while retaining the ability to process high-resolution data when required
3Use of energy by moving object
If the internal pixel clock frequency is reduced to lower power consumption, then power usage is reduced, but the processing time may be insufficient
Solution Approach 1:
The patent applies dynamics by making the pixel clock frequency adjustable rather than fixed. The timing controller can dynamically change the pixel clock frequency based on the actual image processing requirements and workload, allowing the system to operate at lower frequencies when possible to reduce power consumption while maintaining the capability to operate at higher frequencies when handling high-resolution data
Solution Approach 2:
The patent changes the frequency parameter of the pixel clock from a fixed high value to a variable parameter that can be adjusted according to actual needs. By modifying the frequency parameter dynamically, the system achieves lower power consumption during normal operation while retaining the ability to process high-resolution data when required
Data Source
AI summary
A timing controller may reduce power consumption and/or reduce influence on wireless communication. A line memory is capable of retaining at least pixel data of one line. An input interface circuit is used for receiving pixel data and storing the pixel data in the line memory. A frequency synthesizer is used for receiving the external pixel clock CKP received by the input interface circuit and generating an internal pixel clock CKINT having frequency being a coefficient K multiplied by frequency of the external pixel clock CKP. An image processing circuit is used for processing the pixel data stored in the line memory synchronously with the internal pixel clock CKINT.


