Timing Controller Pulse Validation for Stable Display Blank Periods
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Solution Overview
Problem
Abnormally generated data enable signals can cause momentary display of incorrect images on flat-panel displays, reducing display quality by applying image data during intended blank periods.
Innovation Solution
A timing controller with a count control circuit, pulse width detector, and pulse generator that counts and compares pulse periods, generating output pulses one-third the length of detected previous pulses to stabilize blank periods and prevent incorrect image display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the timing controller directly applies image data during the effective period of the data enable signal, then the display operates normally during valid image periods, but abnormal images are displayed during blank periods when the data enable signal is abnormally generated with logic high level
Solution Approach 1:
The timing controller performs preliminary detection of the data enable signal period before applying image data. By detecting whether the current period matches the expected period in advance, the controller prevents abnormal images from being displayed during blank periods, thereby improving display reliability without requiring complex post-processing mechanisms
Solution Approach 2:
The timing controller introduces an intermediate period detection mechanism between the data enable signal and the image data application. This intermediary detection step verifies signal validity before allowing image data to pass through, preventing abnormal signals from causing display errors while maintaining a relatively simple overall system structure
2Speed
If the timing controller generates control signals in response to every pulse of the data enable signal, then the response time is minimized, but abnormal pulses cause incorrect timing and display artifacts
Solution Approach 1:
The timing controller performs preliminary period detection on incoming pulses before generating control signals. By verifying that each pulse has the expected period in advance, the controller ensures timing accuracy is maintained while still responding quickly to valid pulses, preventing abnormal pulses from causing display artifacts
Solution Approach 2:
The timing control process is segmented into distinct stages: period detection, period validation, and control signal generation. This segmentation allows the system to quickly process valid pulses while filtering out abnormal ones, maintaining both fast response time and high timing accuracy
Data Source
AI summary
A timing controller includes a count control circuit, a pulse width detector, and a pulse generator. The count control circuit receives an external enable signal. Pulses of the external enable signal include an effective and a blank period of image data. The count control circuit counts pulse widths of each of the pulses. The pulse width detector receives the counted pulse widths, compares a pulse width of a present pulse with pulse widths of previous pulses, and detects a pulse width of a previous pulse that has a pulse width smaller than the pulse width of the present pulse. The pulse generator generates three output pulses having pulse widths that are one-third a period of the detected previous pulse. The pulse generator outputs the first, second and third pulses as an internal enable signal.