Timing Controller Pulse Scheduling for OLED Refresh-Rate Flicker

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flicker occurs when switching between different image refresh rates in OLED displays due to differences in threshold-compensated data voltages causing hysteresis effects among driving transistors, leading to display quality issues.

Innovation Solution

A timing controller is introduced with a first and second driving circuit, providing multiple pulses during a refresh frame for data writing and hysteresis reduction, and maintaining these pulses across hold frames to stabilize transistor characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple driving modes with different image refresh rates are used to adapt to different application scenes, then power consumption is reduced and display fluency is improved, but flicker occurs when switching between refresh rates

Engineering Contradiction:
Improveadaptability to different application scenesVSAvoiddisplay stability during refresh rate switching
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent performs preliminary threshold compensation and data voltage writing before the actual display refresh. By pre-compensating the transistor threshold voltages and pre-writing the data voltages to the pixel electrodes during the non-display period, the system ensures that when refresh rate switching occurs, the pixel circuits are already in a stable state, preventing flicker. This is achieved by extending the writing and compensation phases to occur before the display period begins.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic threshold compensation and data writing operations that occur at fixed intervals independent of the display refresh rate. The writing and compensation circuits perform their functions in regular periodic cycles, ensuring that regardless of whether the display is running at 60Hz, 120Hz, or any other refresh rate, the pixel circuits receive consistent periodic treatment that maintains stability during transitions.

Inventive Principle:
Principle #19Periodic action

2Manufacturing precision

If threshold compensation processing is performed during each refresh frame, then display quality is improved, but additional time is required for data writing and compensation operations

Engineering Contradiction:
Improvedisplay qualityVSAvoidtime for data writing and compensation
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent moves the threshold compensation and data writing operations from the temporal dimension (during the display period) to another dimension (the non-display period or idle time). By utilizing the time dimension that would otherwise be unused, the system performs compensation and writing operations without extending the actual display refresh time. This allows high-quality compensation to occur in parallel with or before the display updates, avoiding time loss in the critical display path.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12475846B2Timing controller, display device, and pixel driving method
Publication Date: 2025.11.18 BEIJING BOE TECH DEV CO LTD
  • US12475846B2 patent drawing
  • US12475846B2 patent drawing
  • US12475846B2 patent drawing

AI summary

The present disclosure provides a timing controller applied to a display device, where the display device includes a plurality of pixel circuits, a first driving circuit and a second driving circuit, each of the pixel circuits includes a driving transistor and a writing and compensation circuit; the first driving circuit is configured to sequentially output a first effective level signal to each of first control signal lines, according to a first driving start signal; the second driving circuit is configured to sequentially output a second effective level signal to each of second control signal lines, according to a second driving start signal; and the timing controller is configured to provide the first driving start signal and the second driving start signal during a refresh frame, where the number W of effective pulses in the first driving start signal is more than or equal to 2.