Timing Controller Restore Memory for Power-Gated Register Retention
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Solution Overview
Problem
Existing display technologies face challenges in maintaining setting values stored in registers during power-down states, leading to potential loss and corruption, which affects the functionality of display drivers.
Innovation Solution
A timing controller with a restore memory outside the power gating region is used to store setting values, which are then restored to registers when power is resumed, eliminating the need for data retention flipflops and reducing chip size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data retention flipflops are used to maintain setting values during power-down state, then setting values are preserved, but chip size increases
Solution Approach 1:
The patent extracts the data retention function from the traditional flipflop-based register system and relocates it to an external memory device. The register unit stores setting values during power-up state, and when power-down occurs, the control unit transfers these values to the external memory device which maintains them during power-down state. This separation eliminates the need for complex data retention flipflops within the chip, reducing chip size while preserving setting value integrity.
Solution Approach 2:
The external memory device acts as an intermediary between the register unit and the power-down state. Instead of using internal flipflops to directly retain data during power-down, the system uses the external memory device as a mediator to store and preserve setting values. The control unit manages the transfer of data between the register unit and external memory, enabling reliable data retention without increasing chip size.
2Reliability
If data retention flipflops are used to maintain setting values during power-down state, then setting values are preserved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming data retention flipflops from the active circuit and relocates the retention function to an external memory device that operates independently during power-down state. This extraction eliminates the need for continuous power supply to retention circuits, significantly reducing power consumption while maintaining setting value integrity during power-down periods.
Solution Approach 2:
The system uses periodic action by transferring data from the register unit to the external memory device only when needed (before power-down or when changes occur), rather than maintaining continuous active retention. The control unit manages this periodic transfer, allowing the register unit to enter a low-power state while the external memory device preserves the setting values without consuming significant power.
3Device complexity
If setting values are stored only in registers within power gating region, then circuit is simple, but setting values are lost during power-down state
Solution Approach 1:
The patent segments the storage system into two distinct parts: a simple register unit within the power gating region for active storage during power-up state, and an external memory device for persistent storage during power-down state. This segmentation allows the internal circuit to remain simple while the external memory handles the retention function, preventing setting value loss without complicating the main circuit architecture.
Solution Approach 2:
The control unit performs preliminary action by transferring setting values from the register unit to the external memory device before power-down occurs. This proactive data transfer ensures that setting values are preserved in the external memory before the power gating region enters low-power mode, preventing any loss of information while maintaining circuit simplicity during operation.
Data Source
AI summary
A timing controller is provided. The timing controller includes: a plurality of registers located in a power gating region and configured to store a plurality of setting values; an image processing circuit configured to receive an image signal and perform image processing on the image signal based on the plurality of setting values; a restore memory located outside the power gating region and configured to store the plurality of setting values; and a bus controller configured to receive the plurality of setting values and store the plurality of setting values in the plurality of registers and the restore memory.