Timing Controller Reverse Scanning Synchronization
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Solution Overview
Problem
Existing timing controllers for image display devices face challenges in accommodating non-coincidence between the count of valid driving lines of a display panel and the total count of outputs from the driving section, particularly during reverse scanning, leading to issues like excessive outputs and reduced flexibility in using different resolutions and IC combinations, which hinders cost reduction and shared use of components.
Innovation Solution
A timing controller with a difference measuring unit to calculate the discrepancy between valid driving lines and total outputs, and a signal outputting unit that shifts the timing of the start pulse signal in reverse scanning based on this discrepancy, ensuring proper synchronization and normal display operations regardless of the resolution or output count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the timing controller uses fixed timing for start pulse signals in reverse scanning, then the device complexity is reduced, but the adaptability to different resolutions and IC output counts is worsened
Solution Approach 1:
The patent implements dynamic timing adjustment for start pulse signals in reverse scanning mode. The timing controller automatically calculates and adjusts the timing based on the actual number of output signals from the IC and the display panel resolution, allowing the system to adapt to different combinations without requiring fixed predetermined timing values.
Solution Approach 2:
The patent changes the timing parameter of the start pulse signal dynamically based on the difference between the IC output count and the valid driving line count. By adjusting this parameter according to actual hardware configurations, the system achieves compatibility across different resolutions and IC combinations while maintaining a relatively simple overall structure.
2Adaptability or versatility
If the timing controller accommodates arbitrary combinations of resolutions and IC outputs, then the adaptability is improved, but the device complexity increases due to additional timing adjustment mechanisms
Solution Approach 1:
The timing controller performs self-adjustment by automatically calculating the timing offset based on the difference between IC output count and valid driving line count. This self-service mechanism eliminates the need for external complex adjustment circuits or manual configuration, achieving high adaptability while keeping the device complexity relatively low.
Solution Approach 2:
The patent implements a feedback mechanism where the timing controller receives information about the IC output count and display resolution, then uses this feedback to automatically adjust the start pulse timing in reverse scanning mode. This closed-loop approach enables arbitrary combinations to be supported without proportionally increasing system complexity.
3Reliability
If the start pulse timing in reverse scanning is shifted based on measured difference, then the display normality is improved, but the difficulty of detecting and measuring increases
Solution Approach 1:
The patent introduces an intermediary calculation mechanism that determines the timing offset based on the difference between IC output count and valid driving line count. This intermediary approach simplifies the detection and measurement process by using readily available parameters (output count and resolution) to calculate the required timing adjustment, rather than requiring direct measurement of complex timing relationships.
Data Source
AI summary
A timing controller is provided which is capable of achieving normal image display at a time of reverse scanning in upward and downward directions and right and left directions. In an image display device having a plurality of scanning line driving ICs (Integrated Circuits), a valid line counting section counts a count of valid driving lines based on a DE (Data Enable) signal and DCK (Dot Clock) signal. A cascade signal counting section counts up a total count of outputs from a count of VCK (Vertical Clock) signals including a VSP (Vertical Start Pulse) 2 output signal up to a VSP1 cascade outputting signal VSP1. A calculating section calculates an excessive output of a scanning line driving IC from a difference between the count of valid driving lines and the total count of outputs. A VSP generating section generates and outputs a VSP2 signal at a time shifted from a reference VSP generating time by time being equivalent to the excessive output calculated by the calculating section thus enabling reverse scanning.