Timing Controller Shared-Memory Loading to Reduce Boot Delays

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Solution Overview

Problem

Existing timing controllers face challenges in preventing storage memories from entering energy-saving modes during processor operations, leading to performance degradation such as delayed booting times due to the storage memory's energy reduction modes.

Innovation Solution

A timing controller method that includes loading line data into a shared memory and reading update data from the storage memory to prevent the storage memory from entering energy-saving modes, thereby maintaining system performance by shortening booting times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the storage memory enters energy-saving mode to reduce power consumption, then energy consumption is reduced, but booting time increases due to delayed data access

Engineering Contradiction:

Improveenergy consumptionVSAvoidbooting time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The controller reads update data from the storage memory in advance while the processor is processing line data, before the storage memory would otherwise enter energy-saving mode. This preliminary action ensures data is prepared and available when needed, preventing booting time delays while allowing the storage memory to operate in energy-saving mode during processor operations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The controller continuously reads update data from the storage memory during processor operations, maintaining continuous useful action on the storage memory to prevent it from entering energy-saving mode. This ensures the storage memory remains active and responsive, eliminating booting time delays caused by mode transitions

Inventive Principle:

Principle #20Continuity of useful action

2Reliability

If the controller waits for processor completion before reading update data, then data consistency is maintained, but storage memory enters energy-saving mode causing performance degradation

Engineering Contradiction:

Improvedata consistencyVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The controller performs preliminary reading of update data during processor operations, before the processor completes its work. This timing ensures data consistency since the storage memory state hasn't changed yet, while also maintaining storage memory activity to prevent energy-saving mode entry and preserve system performance

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The controller acts as an intermediary that coordinates between the processor and storage memory operations. It strategically times its read operations to occur during processor execution, utilizing the intermediate period when both components are active, thereby maintaining data consistency while preventing storage memory from entering low-power states

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250316243A1Timing controller and method of driving timing controller

Publication Date: 2025.10.09 LX SEMICON CO LTD

AI summary

A method of driving a timing controller includes requesting, by a processor, first line data from a controller; extracting, by the controller, the first line data from a storage memory and loading the extracted first line data into a shared memory; transferring, by the controller, the first line data loaded into the shared memory to the processor; and reading, by the controller, update data for updating an operation of the storage memory from the storage memory in response to the transfer of the first line data.