Timing Controller IC Start Signal Timing Control

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Solution Overview

Problem

Existing timing controller integrated circuits (TCON IC) require a line buffer to store delayed data signals, increasing costs due to the need for significant storage capacity, especially for high-resolution displays like 1920*1080.

Innovation Solution

The method involves controlling the start signal (STV) timing to be before the input RGB data timing, eliminating the need for a line buffer by processing the low voltage differential signaling (LVDS) signal to generate and synchronize the STV with the vertical synchronization signal, thereby avoiding data loss and storage requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a line buffer is added to delay data signals for synchronization, then the timing synchronization is improved, but the device complexity and cost increase

Engineering Contradiction:

Improvetiming synchronizationVSAvoidline buffer

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The start signal STV is generated in advance before the RGB data arrives at the processing unit. By preliminarily preparing the control signal timing, the system eliminates the need for buffering RGB data, thus avoiding the line buffer while maintaining proper synchronization. The STV signal is advanced relative to the pixel clock to ensure it is ready when data processing begins.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If a line buffer with large storage capacity is disposed to store delayed data signals, then the data signal delay is improved, but the cost increases

Engineering Contradiction:

Improvedata signal delayVSAvoidcost

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The system performs preliminary timing adjustment by advancing the STV signal generation relative to the RGB data input. This preliminary action ensures that control signals are ready before data arrives, eliminating the need for time-consuming data buffering and associated costs.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of delaying the RGB data signals using a line buffer, the invention inverts the approach by advancing the start signal STV timing. Rather than pushing data backward in time through buffering, the control signal is pulled forward, achieving synchronization without storage requirements.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS9898993B2Method for controlling message signal within timing controller integrated circuit, timing controller integrated circuit and display panel

Publication Date: 2018.02.20 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD

AI summary

The present disclosure provides method for controlling a message signal within a timing controller integrated circuit, the timing controller integrated circuit and a display panel. The method includes: receiving a low voltage differential signaling signal; decoding the low voltage differential signaling signal to obtain a transistor-transistor logic RGB data signal and a control signal, wherein the control signal comprises: a start signal, a horizontal synchronization and a vertical synchronization; processing the transistor-transistor logic RGB data signal to obtain an input RGB data; controlling a timing of the start signal before a timing of the input RGB data; and processing the input RGB data to obtain a mini-low voltage differential signaling data. Therefore, the technical scheme provided by the present disclosure has an advantage of the low cost.