Timing Controller Voltage Distribution for LCD Noise Reduction
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Solution Overview
Problem
In liquid crystal display (LCD) apparatuses, the increased number of data driving chips due to higher resolution leads to varying distances between the timing controller and data driving chips, resulting in uneven power requirements, increased power consumption, and noise generation due to differing wire resistances.
Innovation Solution
A timing controller with multiple voltage generators and transmitting terminals that output distinct top and bottom voltages to each data driving chip, allowing for independent power provision based on chip location, thereby reducing power consumption and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a relatively high leveled power is applied to the data driving chip to drive the data driving chip which is disposed relatively far from the timing controller, then the data driving chip can be driven reliably, but a power consumption increases and a noise is generated
Solution Approach 1:
The patent applies local quality by providing different power levels to different data driving chips based on their specific locations and wiring characteristics. The timing controller identifies chips with higher wire resistance (typically those farther away) and provides them with elevated power levels, while chips with lower resistance receive standard power levels. This localized adaptation resolves the contradiction by ensuring reliable operation only where needed, rather than uniformly increasing power to all chips.
2Reliability
If a relatively high leveled power is applied to the data driving chip to drive the data driving chip which is disposed relatively far from the timing controller, then the data driving chip can be driven reliably, but a noise is generated
Solution Approach 1:
The patent reduces noise by applying elevated power levels only to specific data driving chips that require it due to their location and wire resistance characteristics. Chips that are farther from the timing controller and have higher resistance receive higher power to maintain signal integrity, while chips closer to the controller receive standard power levels. This localized approach minimizes unnecessary noise generation while ensuring reliable operation where needed.
3Device complexity
If the timing controller provides uniform power to all data driving chips, then the device complexity is low, but the driving reliability decreases for chips disposed far from the timing controller
Solution Approach 1:
The patent implements feedback by having the timing controller identify and respond to the specific power requirements of each data driving chip based on their location and wiring characteristics. The controller receives information about which chips need elevated power levels and adjusts its output accordingly, providing higher power to distant chips with higher resistance and standard power to closer chips. This feedback mechanism enables adaptive power distribution that maintains reliability without requiring complex manual configuration.
Data Source
AI summary
A timing controller includes: a top voltage generator configured to output first to third top voltages; a bottom voltage generator configured to output first to third bottom voltages; a first transmitting part configured to output a first data signal for a first data driving chip, based on the first top and bottom voltages; a second transmitting part configured to output a second data signal for a second data driving chip based on the second top and bottom voltages; and a third transmitting part configured to output a third data signal for a third data driving chip based on the third top and bottom voltages, where one of the first to third top voltages is different from another of the first to third top voltages, and one of the first to third bottom voltages is different from another of the first to third bottom voltages.