Timing Correction Circuit for Display Data Synchronization
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Solution Overview
Problem
Thin-film transistor-based liquid crystal display modules with built-in driving circuits experience capture errors due to timing delays caused by different wiring configurations for display data and scanning signals, leading to inefficiencies in data transfer.
Innovation Solution
Incorporating a timing correction circuit with adjacent transmission lines for display data and synchronization clock, utilizing the same wiring configuration and number of inverters to synchronize the timing of scanning signals with display data, and employing poly-silicon thin-film transistors for improved mobility and reduced variations in transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different wiring configurations are used for display data and scanning signals, then the layout flexibility is improved, but timing synchronization deteriorates causing capture errors
Solution Approach 1:
A timing correction circuit is introduced as an intermediary component between the shift register and latch circuits. This circuit receives the scanning signal and corrects its timing based on a correction value, acting as a mediator that reconciles the timing mismatch caused by different wiring configurations while maintaining layout flexibility
Solution Approach 2:
The timing correction circuit dynamically adjusts the timing parameter of the scanning signal by adding a correction value to the clock cycle. This parameter change compensates for the timing delay introduced by different wiring configurations, ensuring synchronization without compromising layout flexibility
2Ease of manufacture
If amorphous silicon or poly-silicon is used for thin-film transistor semiconductor layer, then manufacturing ease is improved, but transistor mobility and characteristic consistency deteriorate
Solution Approach 1:
The patent adjusts the timing parameters (clock cycle, correction value) to compensate for the lower mobility and wider variations inherent in amorphous silicon or poly-silicon transistors. By optimizing these parameters, the system achieves reliable operation despite the material limitations
Solution Approach 2:
The timing correction circuit implements a feedback mechanism where the timing of display data and scanning signals is continuously monitored and adjusted. The correction value is determined based on the actual timing relationship, creating a closed-loop system that compensates for transistor variations
3Speed
If inverters are inserted to shorten delay, then signal transmission speed is improved, but timing equality between display data and scanning signal deteriorates due to different wiring configurations
Solution Approach 1:
The timing correction circuit serves as a mediator that receives both the scanning signal and display data, compares their timing, and applies selective correction to the scanning signal. This intermediary approach achieves timing equality without requiring symmetric inverter insertion in both signal paths
Solution Approach 2:
Instead of applying uniform timing correction to both signal paths, the patent applies correction locally and selectively only to the scanning signal path where timing delay occurs. This localized approach maintains timing equality while avoiding unnecessary complexity in the display data path
Data Source
AI summary
The present invention is to prevent a capture error of display data caused by a delay due to a built-in driving circuit in a display device with a built-in driving circuit. The display device comprises: a display area having a plurality of sub pixels; and a driving circuit formed at the periphery of the display area; wherein the driving circuit includes: a first scanning circuit that performs scanning in a first direction; and a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit; wherein the driving circuit includes a timing correction circuit which corrects the timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external; wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; and wherein a transmission line up to the latch circuit of the display data and a transmission line up to the timing correction circuit of the display data synchronization clock are adjacently arranged.