Timing Data Acquisition Using Multi-Delay Flip-Flop Boundary Detection
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Solution Overview
Problem
Existing timing data acquisition devices face challenges in collecting accurate timing data due to errors from on-chip variation factors and setup time noise in semiconductor devices, particularly when miniaturization requires precise picosecond-scale timing data.
Innovation Solution
A timing data acquisition device is designed with a data signal generator and a clock signal generator that repeatedly delay periodic signals to generate data and clock signals, which are then used by D flip-flops to determine set-up and hold times by identifying pass/fail boundary points, incorporating a cascaded chain of delay units and mode selectors to support different measurement modes and reduce timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing timing data acquisition devices are used, then device complexity is reduced, but measurement precision deteriorates due to errors from on-chip variation and setup time noise
Solution Approach 1:
The device is segmented into multiple independent delay units (first delay unit, second delay unit, third delay unit) that can be individually configured and controlled. Each delay unit processes signals independently, allowing precise control over data and clock signal delays to achieve accurate setup and hold time measurements while isolating error sources
Solution Approach 2:
A delay compensation signal is introduced as an intermediary element to counterbalance timing errors. The compensation signal is generated based on measured timing deviations and applied to offset errors from on-chip variation and setup time noise, thereby improving measurement precision without requiring complete redesign of the core measurement architecture
2Measurement precision
If delay values are increased to improve timing resolution, then measurement precision improves, but loss of time increases due to longer measurement cycles
Solution Approach 1:
The device enables continuous timing measurements by overlapping measurement cycles. While one measurement is in progress with large delay values for precision, the system prepares compensation signals and configures delay units for the next measurement, ensuring that useful action continues without interruption and minimizing idle time between measurements
Solution Approach 2:
The delay units are designed with dynamic, adjustable delay values that can be changed during operation. The system dynamically selects optimal delay values based on measurement requirements - using larger delays when high precision is needed and smaller delays when speed is prioritized, allowing flexible adaptation between precision and measurement cycle duration
Data Source
AI summary
A timing data acquisition device includes a data signal generator, which is configured to generate a plurality of data signals by repeatedly delaying a first periodic timing signal in increments of a first delay value, and a clock signal generator, which is configured to generate a plurality of clock signals by repeatedly delaying a second periodic timing signal in increments of a second delay value exceeding the first delay value. A plurality of D flip-flops are also provided. The flip-flops have: (i) data terminals responsive to respective ones of the plurality of data signals, and (ii) clock terminals responsive to respective ones of the plurality of clock signals. The flip flops are configured to generate a plurality of latched output signals having values that collectively encode at least one of a set-up time and a hold-time of a semiconductor device by identifying a pass/fail boundary point between the delays associated with the plurality of data signals and the delays associated with the plurality of clock signals.