Timing Detection Circuit Multiphase Clock Segmentation
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Solution Overview
Problem
Existing timing detection circuits for synchronizing signals in laser-beam printers and digital copiers face limitations in accuracy and power consumption, with increased frequency leading to instability and larger circuitry increasing power consumption, while current techniques struggle to adjust timing modulation with respect to a reference clock effectively.
Innovation Solution
A timing detection circuit that generates multiphase clocks with different phases and uses a combination of first and second detection circuits to accurately detect the timing of a synchronizing signal with respect to a reference clock, allowing for precise timing adjustment of light beam modulation without excessive frequency increase or circuit size expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency of the high-frequency clock is increased to improve timing detection accuracy, then the accuracy of timing detection is improved, but the power consumption and instability of the semiconductor integrated circuit increase
Solution Approach 1:
The patent divides the timing detection process into two stages: first-stage timing detection using a high-frequency clock to achieve high accuracy, and second-stage timing detection using a video clock to reduce power consumption. This segmentation allows the system to benefit from high-frequency operation only when necessary for initial precision, while using lower-frequency operation for subsequent adjustments, thereby resolving the contradiction between timing detection accuracy and power consumption.
2Measurement precision
If the frequency of the high-frequency clock is increased to improve timing detection accuracy, then the accuracy of timing detection is improved, but the stability of the semiconductor integrated circuit deteriorates
Solution Approach 1:
The patent segments the timing detection operation into two phases: initial high-frequency timing detection for accuracy, followed by video clock-based detection for stability. By limiting high-frequency operation to only the first stage, the system achieves the necessary timing precision without subjecting the semiconductor circuit to prolonged high-frequency stress that would cause instability and reliability issues.
3Measurement precision
If multiple multiphase clocks are generated and compared with the synchronizing signal to improve timing detection accuracy, then the accuracy of timing detection is improved, but the size of the circuitry increases
Solution Approach 1:
The patent segments the clock comparison process into two stages: first-stage comparison using multiple multiphase clocks at high frequency for accurate timing detection, and second-stage comparison using a single video clock for final timing adjustment. This segmentation reduces the need for multiple continuous high-frequency clock comparisons, thereby reducing circuit size while maintaining timing detection accuracy.
Solution Approach 2:
The patent dynamically switches between different clock frequencies and comparison methods based on the detection stage. In the first stage, multiple multiphase clocks are used for high-accuracy detection; in the second stage, the system transitions to using a single video clock for final timing adjustment. This dynamic adaptation allows the circuit to achieve high accuracy when needed while minimizing circuit size during routine operation.
4Measurement precision
If the size of the circuitry is increased to generate and compare multiple multiphase clocks, then the accuracy of timing detection is improved, but the power consumption increases
Solution Approach 1:
The patent segments the timing detection process into two stages with different resource requirements: first-stage detection using multiple multiphase clocks for high accuracy, and second-stage detection using a single video clock for power-efficient final adjustment. This segmentation allows the system to achieve high timing detection accuracy only when necessary while minimizing power consumption during routine operation.
Solution Approach 2:
The patent dynamically adjusts the circuit configuration based on the detection stage. During first-stage timing detection, the circuit activates multiple multiphase clock generators and comparators to achieve high accuracy. During second-stage detection, the system dynamically transitions to using only the video clock, reducing circuit activity and power consumption while maintaining timing accuracy.
Data Source
AI summary
A timing detection circuit including a first timing detection circuit, a second detection circuit, and an output circuit is disclosed. The first detection circuit detects, among multiphase clocks having n mutually different phases and a frequency of k times the frequency of a reference clock, a closest clock having a clock edge closest to a valid edge of the synchronizing signal and generates first detect signal DET_A indicating the detected clock. The second timing detection circuit detects within which of k successive cycles of the representative clock selected from the multiphase clocks the valid edge of the synchronizing signal is positioned and generates second detect signal DET_B indicating the detected cycle. The output circuit receives the first detect signal and the second detect signal and outputs first output signal OUT_A and second output signal OUT_B.