Timing Domain Transfer Circuit With Feedback Event Handshake
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Solution Overview
Problem
Signals are often lost or misaligned during transfers between different timing domains in electronic systems due to clock rate or phase differences, leading to operational issues and misalignment of command and data sequences.
Innovation Solution
A timing domain transfer circuit that uses feedback mechanisms to confirm successful transfer of events between timing domains, ensuring events are not lost or duplicated, by operating based on feedback signals independent of the clock domains and using pulse generators to manage reset pulses effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signals are transferred between timing domains with different clock rates or phases, then components can operate at optimized internal frequencies, but signals may be lost or misaligned during transfer
Solution Approach 1:
The patent uses feedback mechanisms where the receiving domain sends acknowledgment signals back to the transmitting domain to confirm successful signal reception. This feedback loop allows the system to detect and correct transfer issues, ensuring reliable signal transfer between timing domains with different clock rates while maintaining optimized component operation.
Solution Approach 2:
The patent introduces intermediate buffering mechanisms and timing domain interface circuits that act as mediators between domains with different clock rates. These intermediaries temporarily store signals and coordinate transfer timing, preventing signal loss while allowing components to operate at their optimized frequencies.
2Speed
If a signal is lost during timing domain transfer, then the transfer process is simple and fast, but all subsequent signals become misaligned with the expected sequence
Solution Approach 1:
Feedback acknowledgment signals confirm successful reception of each command before the next is processed. If a signal is lost, the feedback mechanism detects the misalignment and triggers corrective actions such as retransmission or sequence reset, preventing cascading errors while maintaining fast transfer speeds for successful signals.
Solution Approach 2:
The system performs preliminary validation and sequencing checks before signal transfer to ensure proper alignment. By preparing and verifying the expected sequence in advance, the system can quickly detect and correct lost signals without disrupting the overall fast transfer rate of valid commands.
3Device complexity
If a signal is transferred more than once between timing domains, then the transfer mechanism is simple, but the signal sequence becomes corrupted and information is lost
Solution Approach 1:
Acknowledgment feedback signals confirm when a transferred signal has been successfully received and processed. This feedback mechanism prevents duplicate processing by informing the transmitting domain that the signal has already been delivered, maintaining sequence integrity without requiring complex transfer mechanisms.
Solution Approach 2:
The patent uses signal copying and comparison techniques where duplicate signals are detected and identified as retransmissions. By comparing incoming signals against expected sequences and using feedback to track transferred signals, the system can identify and discard duplicate copies while maintaining simple transfer mechanisms.
Data Source
AI summary
Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.