Timing-Driven Clock Tree Synthesis for Skew and Timing Closure
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Solution Overview
Problem
Conventional clock tree synthesis in microdevice design often results in unbalanced clock trees due to transmission delays, leading to clock skew and synchronization issues between clock-driven circuits, which are not adequately addressed by existing methods that prioritize global skew correction over timing closure.
Innovation Solution
The implementation of timing-driven clock tree synthesis tools that perform static timing analysis to determine data and clock arrival timings, allowing for initial balancing of the clock tree based on slack metrics, rather than solely correcting for global skew, thereby optimizing the clock tree to synchronize data signal arrival times with clock signal arrival times at clock-driven circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock tree synthesis prioritizes global skew correction, then clock synchronization across the circuit is improved, but timing closure is delayed and the number of balancing iterations increases
Solution Approach 1:
The patent performs preliminary timing analysis before clock tree synthesis to determine data arrival times at flip-flops. This advance knowledge allows the clock tree synthesis to directly target timing-critical paths first, rather than performing multiple iterative skew corrections. The clock arrival times are specifically adjusted based on pre-calculated data arrival times, enabling timing closure to be achieved faster while maintaining clock synchronization.
2Reliability
If conventional clock tree synthesis performs multiple balancing iterations, then clock skew is reduced, but the synthesis process complexity and time increase
Solution Approach 1:
The patent changes the approach by using timing-driven parameters (data arrival times, required clock arrival times, slack values) to directly guide clock tree synthesis. Instead of relying on multiple iterative skew corrections, the method calculates optimal clock arrival times based on timing analysis results and applies these parameters in a single pass or minimal iterations, thereby reducing synthesis process complexity while achieving the same clock skew reduction.
3Loss of time
If conventional clock tree synthesis uses assumed characteristic speeds, then preliminary timing estimates are obtained quickly, but timing accuracy is insufficient for optimal clock tree balancing
Solution Approach 1:
The patent performs preliminary static timing analysis to calculate accurate data arrival times at each flip-flop before conducting clock tree synthesis. This preliminary action provides precise timing information that guides the clock tree synthesis process, eliminating the need for multiple iterations and assumed characteristic speeds. The method achieves both speed and accuracy by doing the timing analysis once in advance and using those results to directly drive the clock tree optimization.
Data Source
AI summary
This application discloses performing a static timing analysis on a circuit design with an unbalanced clock tree, for example, to determine data arrival timing and clock arrival timing at multiple clock-driven circuits in a circuit design, and then performing clock tree synthesis on the circuit design to initially balance the unbalanced clock tree based, at least in part, on the data arrival timing relative to the clock arrival timing at the multiple clock-driven circuits. The clock tree after initial balancing includes a clock signal path configured to provide a clock signal to each of the multiple clock-driven circuits with a new clock arrival timing that corresponds to the data arrival timing.