Timing Edge Tracking for Crosstalk Analysis Pessimism Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional computer-automated electronic design analysis systems face pessimism in crosstalk analysis due to the use of timing windows, which create unrealistic scenarios due to on-chip variation and merging of paths, leading to inaccurate results.

Innovation Solution

The method involves tracking and encoding timing edges instead of timing windows, allowing for separate analysis of maximum and minimum delays, and using bit vectors to compactly represent switching edges, thereby reducing pessimism in crosstalk analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If timing windows are used for crosstalk analysis, then all possible paths are covered, but pessimism increases and accuracy decreases

Engineering Contradiction:
Improvecrosstalk analysis accuracyVSAvoidtiming analysis accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent segments the continuous timing window into discrete timing edges represented by bit vectors. Instead of analyzing all paths within a timing window, the method identifies and tracks specific timing edges (arrival times) of signals. This segmentation allows precise comparison of aggressor and victim net edges without the pessimism of covering all possible paths, thereby improving accuracy while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter representation from continuous timing windows to discrete timing edges encoded as bit vectors. By representing arrival times as specific parameter values (bit positions in vectors) rather than continuous ranges, the method enables precise edge-to-edge comparison. This parameter transformation eliminates the pessimism inherent in window-based analysis while ensuring all critical timing scenarios are captured.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If all possible path combinations are analyzed, then complete coverage is achieved, but computational complexity increases

Engineering Contradiction:
Improveanalysis completenessVSAvoidcomputation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by pre-computing and storing timing edges for all paths in bit vector format before crosstalk analysis. The earliest and latest arrival edges are identified and encoded in advance, creating a compact representation that captures all critical timing information. This preliminary encoding enables efficient O(1) comparison during actual analysis without requiring exhaustive path enumeration at runtime.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates compact bit vector copies of timing information that represent entire sets of path arrivals. Instead of storing or processing actual path combinations, the method uses bit vectors as compressed copies where each bit position represents a timing edge. This copying approach maintains complete analysis coverage while dramatically reducing computational complexity through efficient bit-wise operations.

Inventive Principle:
Principle #26Copying

3Quantity of substance

If timing windows are used, then storage is simplified, but infinite storage may be required for complete path coverage

Engineering Contradiction:
Improvestorage efficiencyVSAvoidpath coverage completeness
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent discards the continuous timing window representation and recovers only the critical discrete timing edges. By identifying and retaining only the earliest and latest arrival edges (and intermediate edges where relevant) as bit positions, the method eliminates the need to store infinite or continuous timing information. This discarding of non-critical data while recovering essential edges achieves complete path coverage with finite, efficient storage.

Inventive Principle:
Principle #34Discarding and recovering

Solution Approach 2:

The patent transforms the storage parameter from continuous timing window ranges to discrete bit positions representing specific arrival times. This parameter change compresses potentially infinite storage requirements into finite bit vectors where each bit represents a specific timing edge. The transformation maintains complete coverage information while enabling efficient finite storage through discrete encoding of critical timing parameters.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9026965B2Arrival edge usage in timing analysis
Publication Date: 2015.05.05 SYNOPSYS INC
  • US9026965B2 patent drawing
  • US9026965B2 patent drawing
  • US9026965B2 patent drawing

AI summary

A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing impacts. To reduce pessimism of crosstalk analysis for a victim net, arrival edges are tracked for the victim net. The switching times of the aggressor net are compared to the edges of the victim net during crosstalk analysis.