Timing Error Detection Circuit With Adaptive Clock Correction
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Solution Overview
Problem
Existing timing error detection and correction systems in integrated circuits face challenges such as meta-stability issues, require extra hold padding, and have limited timing error detection windows, leading to increased power consumption and area overhead.
Innovation Solution
A timing error detection and correction circuit that uses transition detectors to monitor critical nodes within a 20% timing window of the clock period, allowing for clock gating or stretching to correct errors without additional buffering, thereby reducing power consumption and increasing detection window breadth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Razor flip-flops use dynamic detection and correction with shadow latch, then timing error detection capability is improved, but area overhead and power consumption increase
Solution Approach 1:
The patent extracts only the essential timing error detection function from the full Razor flip-flop structure. Instead of implementing complete shadow latches for every flip-flop, the invention selectively places transition detectors at critical nodes in the data path, removing unnecessary circuitry while preserving timing error detection capability.
Solution Approach 2:
The patent segments the timing error detection function into distributed transition detectors placed at specific critical nodes throughout the data path, rather than using a monolithic shadow latch structure. This segmentation allows parallel detection of timing errors at multiple points simultaneously, improving coverage while reducing overall area overhead.
2Reliability
If Razor flip-flops use double sampling with delayed clock, then timing violation detection is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic sampling at critical nodes using transition detectors that monitor for unwanted transitions during the clock period. Instead of continuous monitoring or double sampling with delayed clocks, the system performs periodic detection at strategically chosen moments, reducing power consumption while maintaining timing violation detection capability.
3Stability of the object's composition
If Razor flip-flops require extra hold padding with additional buffers, then metastability problems are reduced, but area overhead and power consumption increase
Solution Approach 1:
The patent applies preliminary timing analysis during design to identify critical nodes where timing violations are most likely to occur. Transition detectors are placed at these predetermined locations before the circuit operates, allowing the system to proactively detect timing errors without requiring additional hold padding buffers that would increase area and power overhead.
4Measurement precision
If timing error detection window is limited in conventional systems, then detection precision is maintained, but detection window breadth decreases
Solution Approach 1:
The patent extends the detection capability from a single time window to multiple dimensions by placing transition detectors at multiple critical nodes throughout the data path. Each detector monitors its local region with high precision, and collectively they provide broad coverage across the entire circuit, effectively adding a spatial dimension to the timing error detection window.
Data Source
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AI summary
An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The nodes are selected during the design according to a desired timing window to be monitored. The error detection circuit flags an error if a transition occurs during a snapshot corresponding to a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock. The timing correction circuit is further configured to adapt the system clock in response to an error being detected.