Timing Error Detection Circuit With Delayed Clock Correction
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Solution Overview
Problem
Existing timing error detection and correction systems in integrated circuits face challenges such as meta-stability issues, require extra hold padding, and have limited timing margin, leading to increased power consumption and area overhead, while also being dependent on replica circuits that can introduce mismatches and reduce power-performance efficiency.
Innovation Solution
A timing error detection and correction circuit that includes a clock unit providing a delayed reference clock, transition detectors, an error detection circuit, and a timing correction circuit capable of adapting the system clock by clock gating or stretching, which monitors critical nodes towards the end of the clock cycle to detect and correct timing errors without relying on replica circuits, thereby reducing power consumption and increasing robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Razor flip-flops with shadow latch and double sampling are used for timing error detection, then timing error detection capability is improved, but area overhead and power consumption increase due to extra hold padding and additional buffers
Solution Approach 1:
The patent extracts the timing error detection function from the traditional double sampling approach and implements it using a single flip-flop with a timing detection circuit that monitors the data path delay. This eliminates the need for shadow latches and additional buffers, reducing area overhead while maintaining timing error detection capability.
Solution Approach 2:
The timing detection circuit in the patent serves multiple functions: it detects timing errors, measures data path delay, and generates correction signals, replacing the separate shadow latch and buffer structures used in traditional approaches. This multi-functionality reduces the overall area required for timing error detection.
2Stability of the object's composition
If Razor flip-flops with extra hold padding using additional buffers are used, then meta-stability problems are reduced, but power consumption increases
Solution Approach 1:
The patent removes the additional buffers required for hold padding and instead uses a timing detection circuit that monitors the actual data path delay. This extraction of the hold padding function eliminates the associated power consumption while maintaining meta-stability immunity through active timing monitoring and correction.
Solution Approach 2:
The patent implements a feedback mechanism where the timing detection circuit continuously monitors the data path delay and generates correction signals to adjust the clock timing. This feedback approach provides dynamic meta-stability protection without the static power overhead of additional buffers.
3Reliability
If Razor flip-flops with delayed clock and shadow flip-flop are used, then timing error detection is improved, but device complexity increases
Solution Approach 1:
The patent extracts the timing error detection function from the complex shadow flip-flop structure and implements it using a simplified timing detection circuit that monitors the data path. This extraction maintains timing error detection accuracy while significantly reducing circuit complexity.
Solution Approach 2:
Instead of using a full shadow flip-flop copy, the patent uses a timing detection circuit that copies only the essential timing monitoring function. This selective copying maintains detection accuracy while reducing the complexity overhead associated with full shadow latch implementation.
4Reliability
If traditional timing error detection systems with replica circuits are used, then timing error detection is enabled, but power-performance efficiency decreases due to mismatches and overhead
Solution Approach 1:
The patent extracts the timing error detection function from replica circuits and implements it directly in the data path using a timing detection circuit. This eliminates the power overhead and mismatches associated with replica circuits while maintaining timing error detection functionality.
Solution Approach 2:
The timing detection circuit in the patent monitors and corrects timing errors within the actual data path without requiring separate replica circuits. This self-service approach eliminates the power-performance efficiency loss associated with maintaining and synchronizing replica circuits.
Data Source
AI summary
An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.