Timing Exception Path Analysis for Accurate At-Speed Test Responses
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Solution Overview
Problem
Conventional stuck-at scan patterns are insufficient for ensuring high product quality in nanometer technologies due to issues like resistive bridges, power drops, and cross-talk noise, which require at-speed testing to detect subtle timing changes, and fail to accurately account for timing exception paths that can lead to false failures and inaccurate circuit simulation results.
Innovation Solution
The method involves applying scan patterns over multiple time frames to identify and mask unknown values at the end points of timing exception paths, which are determined by analyzing design constraints and sensitization checks, ensuring accurate propagation and response generation in the presence of timing exception paths such as false, multi-cycle, and conditional paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If at-speed scan patterns are applied to detect subtle timing changes, then measurement precision is improved, but false failures occur due to timing exception paths
Solution Approach 1:
The patent applies preliminary action by performing static timing analysis before at-speed testing to identify timing exception paths. The methodology pre-characterizes multi-cycle paths and false paths, then uses this information to guide the test application process, allowing the system to account for known timing exceptions when evaluating test results.
Solution Approach 2:
The patent introduces an intermediary layer of timing exception path analysis that mediates between the test pattern application and response evaluation. By inserting this intermediate analysis step, the system can distinguish between legitimate failures and expected behavior on timing exception paths, preventing false failures from corrupting the overall test results.
2Device complexity
If timing exception paths are ignored in simulation, then device complexity is reduced, but simulation accuracy deteriorates
Solution Approach 1:
The patent applies local quality by selectively handling timing exception paths rather than uniformly analyzing all circuit paths. The methodology identifies specific regions (timing exception paths) that require special handling, while leaving the rest of the circuit simulation unchanged. This localized approach maintains simulation accuracy for critical paths without unnecessarily increasing overall simulation complexity.
3Reliability
If scan patterns exercise all circuit paths, then test coverage is improved, but unknown states increase due to sensitized timing exception paths
Solution Approach 1:
The patent extracts timing exception path information from the overall circuit analysis and handles it separately. By isolating multi-cycle paths and false paths into a distinct analysis category, the methodology can account for their unique timing behavior without allowing them to contaminate the analysis of normal single-cycle paths, thereby reducing the propagation of unknown states.
Data Source
AI summary
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.