Timing Generation Circuit for Semiconductor Storage Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor storage devices, random variations in transistor characteristics lead to inaccurate timing replication, necessitating unnecessary timing margins, which result in lower operating frequencies and increased power consumption, and fail to satisfactorily replicate optimal timing due to changes in random variations or power supply voltage fluctuations.
Innovation Solution
A timing generation circuit that selects a timing in a preset order from the distribution of bit line signal changes to activate sense amplifiers, using a combination of timing selection circuits and a timing multiplier to generate activation timing based on the selected timing, ensuring optimal activation even with varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing margins are increased to guarantee functionality due to transistor variations, then reliability is improved, but operating frequency decreases and power consumption increases
Solution Approach 1:
The timing generation circuit dynamically adjusts the sense amplifier activation timing based on detected bit line delay characteristics. Instead of using fixed worst-case timing margins, the circuit adapts timing to actual operating conditions, allowing optimization of operating frequency while maintaining reliability across different transistor variation scenarios
Solution Approach 2:
The circuit incorporates feedback mechanisms that detect actual bit line delay times and use this information to adjust sense amplifier activation timing. This feedback loop enables the system to replicate optimal timing accurately despite transistor variations, eliminating the need for excessive static timing margins
2Reliability
If timing margins are increased to guarantee functionality, then reliability is improved, but power consumption increases
Solution Approach 1:
The timing generation circuit dynamically adjusts activation timing based on actual bit line delay detection, enabling the system to use minimum necessary timing margins rather than fixed worst-case margins. This dynamic adaptation reduces unnecessary power consumption while maintaining functionality across transistor variations
Solution Approach 2:
The circuit changes the timing parameter of sense amplifier activation based on detected bit line delay characteristics. By adjusting this parameter dynamically rather than using fixed conservative values, the system reduces power consumption while ensuring reliable operation under varying transistor conditions
3Device complexity
If fixed timing is used to simplify design, then device complexity is reduced, but accuracy of timing replication decreases due to transistor variations and power supply fluctuations
Solution Approach 1:
The timing generation circuit uses feedback from actual bit line delay detection to adjust sense amplifier activation timing. This feedback mechanism enables accurate timing replication despite transistor variations and power supply fluctuations, achieving high precision without excessive complexity
Solution Approach 2:
The circuit performs self-adjustment by detecting its own timing characteristics and automatically correcting for variations. This self-service capability enables the system to maintain high timing accuracy without requiring complex external calibration or adjustment mechanisms
Data Source
AI summary
According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided in intersection portions of the plurality of word lines and the plurality of bit lines. The plurality of sense amplifiers is configured to detect a signal level of the corresponding bit lines. The timing generation circuit includes a timing selection circuit configured to select a timing in a preset order from among timings in which each bit line signal in the plurality of bit lines changes. The timing generation circuit is configured to generate activation timing to activate the plurality of sense amplifiers based on the selected timing.