Timing Generator With Edge Masking for Arbitrary Pulse Widths
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Solution Overview
Problem
Existing timing generators for depth-imaging devices, particularly in time-of-flight (TOF) sensing, face challenges in achieving high resolution for pulse widths and precise placement of rising and falling edges of timing signals, which is crucial for accurate distance measurement and three-dimensional imaging applications.
Innovation Solution
A timing generator system comprising a coarse delay circuit, a fine delay circuit, an edge combiner, and a masking circuit, which allows for the generation of timing signals with rising and falling edges placed with a resolution finer than a clock period, achieving pulse widths less than and greater than the clock period, and enabling arbitrary pulse widths by controlling the clock period through masking mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional timing generator uses a single delay circuit operated at a fixed clock period, then the device complexity is low, but the timing resolution cannot be finer than the clock period and pulse widths cannot be arbitrarily controlled
Solution Approach 1:
The timing generator is divided into multiple independent delay circuits (first delay circuit, second delay circuit, third delay circuit, fourth delay circuit) each operating at different clock periods. This segmentation allows each circuit to contribute differently to the final timing signal, enabling resolution finer than any single clock period while maintaining manageable complexity through modular design.
Solution Approach 2:
The multiple delay circuits serve multiple functions: they generate timing signals at different resolutions, provide arbitrary pulse width control through selective combination, and enable both rising and falling edge manipulation. This multi-functionality achieves high timing resolution without proportionally increasing device complexity.
2Measurement precision
If the clock period is reduced to achieve finer timing resolution, then the timing resolution improves, but the pulse width control becomes limited and cannot achieve arbitrary widths
Solution Approach 1:
The system dynamically selects and combines timing signals from different delay circuits based on desired pulse width requirements. The edge combiner circuit dynamically adjusts which rising and falling edges are combined, allowing arbitrary pulse widths to be constructed from finer resolution timing components, thus achieving both high resolution and adaptability.
Solution Approach 2:
The system changes the effective clock period parameter by selectively combining signals from circuits operating at different clock periods. This allows the output to achieve timing resolution finer than any individual clock period while maintaining the ability to generate arbitrary pulse widths through parameter manipulation.
3Measurement precision
If multiple delay circuits operating at different clock periods are used to achieve high resolution and arbitrary pulse widths, then the timing resolution and adaptability improve, but the device complexity increases
Solution Approach 1:
Multiple timing signals from different delay circuits are merged by the edge combiner circuit. This combining approach allows the system to achieve high timing resolution and arbitrary pulse width control by synthesizing the strengths of multiple circuits, while the merging process itself is implemented through standard logic circuitry that minimizes additional complexity.
4Adaptability or versatility
If the rising edge and falling edge are controlled independently to achieve arbitrary pulse widths, then the adaptability improves, but the device complexity increases due to separate control mechanisms
Solution Approach 1:
The control of rising and falling edges is segmented into separate delay circuits (first and second for rising edges, third and fourth for falling edges). This segmentation allows independent manipulation of each edge while using identical circuit architectures, achieving high control flexibility without proportionally increasing overall complexity through repetition of proven designs.
Data Source
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AI summary
An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.