Timing Signal Generator for Non-Integer Multi-Period Synchronization
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Solution Overview
Problem
Existing timing signal generators lack the capability to provide finer timing resolution and synchronization across multiple time periods, limiting their ability to accurately coordinate activities in large electronic systems.
Innovation Solution
A system comprising a master period generator with resettable counters, memory for storing period values, and a match detector circuit to determine residue values, allowing for non-integer timing signal generation and synchronization across multiple time periods, enabling precise timing edge placement and higher resolution sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a system uses integer multiples of system clock cycles for timing signals, then the system is simple to manufacture and operate, but the timing resolution is limited to clock cycle granularity
Solution Approach 1:
The timing signal generation is segmented into two independent components: an integer counter that counts whole clock cycles and a residue register that stores fractional clock cycle values. This segmentation allows the system to achieve sub-clock-cycle timing resolution by combining integer cycle counting with fractional residue values, thereby improving timing precision without requiring a complete redesign of the timing generation architecture.
Solution Approach 2:
A residue register acts as an intermediary component between the integer counter and the final timing signal output. The residue register stores fractional clock cycle values that are added to the integer counter output, serving as a mediator that enables fine timing adjustment without directly modifying the clock signal path or requiring complex phase-locked loop circuitry.
2Adaptability or versatility
If timing signals are generated using traditional counter methods, then the system architecture is simple, but the ability to provide synchronized timing across multiple time periods is limited
Solution Approach 1:
The timing generator is designed with universal components that can serve multiple functions: the same integer counter and residue register architecture can generate timing signals for different time periods by simply loading different period values into the counter. This multi-functionality allows a single hardware design to support various timing requirements without requiring separate dedicated circuits for each time period, thereby improving adaptability while controlling complexity.
Solution Approach 2:
Period values and residue values are pre-loaded into the counter and residue register before timing signal generation begins. This preliminary action allows the system to quickly switch between different time periods by simply loading new values without complex recalculation during operation, enabling flexible multi-period synchronization while maintaining a relatively simple hardware architecture.
3Measurement precision
If finer timing resolution is achieved through additional circuitry, then timing precision improves, but transmission line inaccuracies and signal distortion increase
Solution Approach 1:
The patent replaces traditional mechanical or analog timing adjustment mechanisms with a digital implementation using counters and residue registers. By using digital logic to generate fine timing adjustments through residue value addition, the system achieves precise timing edge placement without requiring complex analog circuitry or long transmission lines, thereby minimizing the impact of transmission line inaccuracies and signal distortion.
Data Source
AI summary
A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations.