Timing Recovery Lock Detection Using Sample Difference Monitoring
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Solution Overview
Problem
Conventional timing recovery systems are inefficient and unreliable in detecting synchronization under impairments such as ISI, noise, large clock offset, and jitter.
Innovation Solution
A timing recovery lock detector circuit that generates two samples and computes their difference to determine the timing recovery status, using either a phase detector (PD) or a phase-frequency detector (PFD) for clock extraction, and is independent of channel conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional Gardner phase detector is used for timing recovery, then timing error detection can be performed, but the system requires high sampling rate (2 samples per symbol) and the lock detector level setting depends on noise and inter symbol interference
Solution Approach 1:
The patent segments the timing recovery process into two distinct sampling phases: a sampling phase (SP) for timing error detection and a lock detector sampling phase (LDSP) for lock detection. This segmentation allows each phase to be optimized independently, enabling accurate timing error detection while using a lower effective sampling rate for lock detection, thus resolving the contradiction between measurement precision and device complexity.
2Reliability
If conventional timing recovery systems monitor signal/constellation points in a certain region with predetermined lock detector threshold, then lock detection can be performed, but the system is not sensitive to channel impairments and may fail when signal is not well equalized
Solution Approach 1:
The patent changes the parameter used for lock detection from fixed signal/constellation point monitoring with predetermined thresholds to dynamic timing error magnitude monitoring. The lock detector compares the magnitude of timing errors against a threshold that adapts to channel conditions, enabling reliable lock detection that is sensitive to channel impairments and works effectively even when the signal is not perfectly equalized.
3Reliability
If conventional timing recovery systems use sophisticated algorithms including advanced timing phase detection, TR equalization, and TR lock detection, then timing recovery can be achieved, but the system becomes complex and inefficient under impairments such as ISI, noise, large clock offset, and jitter
Solution Approach 1:
The patent extracts the lock detection function from the complex conventional timing recovery system and implements it as a separate, simplified module. Instead of relying on sophisticated algorithms that monitor signal/constellation points, the patent extracts timing error magnitude information and uses simple threshold comparison for lock detection, thereby reducing algorithm complexity while maintaining or improving reliability under impairments.
4Productivity
If lock detector level is set according to predetermined threshold in conventional systems, then lock detection can be announced when threshold is crossed, but the setting depends on noise and inter symbol interference making it inefficient
Solution Approach 1:
The patent implements feedback by using the timing error detector characteristic (TEDC) to dynamically inform the lock detector about the current timing error magnitude. The lock detector level is set based on feedback from the timing error measurements rather than being a fixed predetermined value, making the lock detection more efficient and reliable by adapting to actual channel conditions including noise and inter symbol interference.
Data Source
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AI summary
A timing recovery lock detector circuit for a signal receiver apparatus is configured to receive a quantised signal from an analog-to-digital convertor, the quantised signal having a periodic unit interval (UI); generate at least one sample at a sampling point in the range of T= -0.25 UI to T= +0.25 UI of the quantised signal; perform a subtraction operation between two samples generated from the quantised signal; increment a timing lock counter if a result of the subtraction operation is positive; increment a reset counter if the result of the subtraction operation is negative, and reset the timing lock counter if the reset counter is above a reset threshold value; determine, if the timing lock counter is above a lock threshold value, that a timing recovery circuit of the signal receiver apparatus is locked; and generate an output signal in response to determining that the timing recovery circuit is locked.