Selective Timing Margin for Untestable IC Paths
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Solution Overview
Problem
Current methods for identifying integrated circuit chips that do not meet performance specifications due to parametric variations are inadequate, as they often fail to test all critical paths, leading to potential sub-standard performance that may not be detected until system test or field use.
Innovation Solution
Integrating statistical timing and automatic test pattern generation to selectively add timing margin to untestable paths during the chip design process, allowing for the identification and optimization of these paths to ensure compliance with performance specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If statistical timing techniques are used to optimize each path in the presence of manufacturing variation, then design performance is improved, but testing coverage is reduced leaving some timing requirements untested
Solution Approach 1:
The patent segments the testing approach by dividing paths into two categories: those testable by at-speed manufacturing test and those that are not. This segmentation allows different handling strategies - statistical timing for testable paths and enhanced static analysis with timing margin for untestable paths - thereby resolving the contradiction between optimization and coverage.
Solution Approach 2:
The patent applies partial action by selectively adding timing margin only to untestable paths rather than all paths. Static timing analysis is performed with enhanced effort on specific untestable paths, providing sufficient testing coverage without the excessive cost of testing every possible path, thus balancing reliability and resource constraints.
2Productivity
If at-speed structural test is used to achieve high coverage with efficient pattern set, then testing efficiency is improved, but certain faults remain difficult or impossible to test
Solution Approach 1:
The patent introduces static timing analysis with timing margin as an intermediary between at-speed structural test and final design validation. This intermediary step identifies and flags untestable paths that escape at-speed testing, providing an additional layer of verification without significantly increasing manufacturing test complexity.
Solution Approach 2:
The patent implements feedback by using results from static timing analysis to identify untestable paths, then feeding this information back into the design process to add timing margin to those specific paths. This closed-loop approach ensures that limitations of at-speed testing are compensated for through targeted static analysis.
Data Source
AI summary
A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.