Timing Marker System for Adaptive Integrated Circuitry Synchronization
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Solution Overview
Problem
Adaptive computing architectures face challenges in controlling data flow processing, particularly in synchronizing multiple tasks within a data stream, especially in applications like WCDMA and cdma2000, where traditional processing control methods differ from the data flow model used in adaptive integrated circuitry.
Innovation Solution
The implementation of a novel timing marker system that designates a specific buffer location for data processing commencement, allowing control over when input data processing begins and ends, and includes a control flow methodology using a programmable node, hardware task manager, and nodal sequencer for synchronization between tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional processing control methods (program instructions, interrupt signals) are used in adaptive computing architecture, then control precision is improved, but device complexity increases due to incompatibility with data flow model
Solution Approach 1:
The patent replaces traditional mechanical control mechanisms (program instructions, interrupt signals) with a data flow-based control system. The data flow controller automatically manages task execution based on data availability and processing status, eliminating the need for complex instruction-based control while maintaining precise control over multiple tasks in the adaptive computing architecture.
2Productivity
If data flow model is used for processing, then productivity is improved through efficient data processing, but difficulty of detecting and measuring synchronization between tasks increases
Solution Approach 1:
The patent implements feedback mechanisms where the data flow controller continuously monitors task status, data availability, and processing progress. This feedback loop enables automatic adjustment of task scheduling and synchronization without complex detection systems, maintaining high productivity while simplifying synchronization management through real-time status awareness and adaptive task coordination.
Data Source
AI summary
The disclosure describes internal synchronization in adaptive integrated circuitry which utilizes a data flow model for data processing. Task initiation and execution are controlled based upon data consumption measured in data buffer units, with initiation of and transitions between tasks based on a determined boundary condition within the data stream. When a data processing task is selected for synchronization, a boundary condition in a data stream is determined for commencement of the selected data processing task. Then, a timing marker for the commencement of the selected data processing task is determined relative to the data stream. The timing marker is dual-valued, providing a designated buffer unit and a designated byte or bit location within the designated buffer. The timing marker is communicated to the selected data processing task, which then commences data processing at a location in the data stream designated by the timing marker.