Timing Model Simplification via Aggressor Path Removal
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Solution Overview
Problem
Establishing a timing model for complex circuits requires significant analysis time or hardware resources, making real-time completion challenging.
Innovation Solution
The method involves identifying victim and aggressor paths, determining transmission delays, and selectively removing aggressor paths and high-fanout circuit devices to simplify the timing model, using a controller to execute these steps and improve analysis efficiency without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large amount of analysis time is used to establish the timing model with high accuracy, then the analysis precision is improved, but the productivity deteriorates
Solution Approach 1:
The patent extracts and removes unnecessary aggressor paths and high-fanout circuit devices from the timing model that do not significantly impact timing analysis accuracy. By selectively eliminating these components, the analysis complexity is reduced while maintaining the essential timing characteristics, thus achieving faster analysis without sacrificing critical accuracy.
Solution Approach 2:
The patent applies partial action by performing timing analysis only on the most critical paths and circuits rather than analyzing the entire circuit comprehensively. By focusing computational resources on victim paths and their immediate aggressors, the method achieves sufficient timing accuracy for decision-making while dramatically reducing overall analysis time.
2Measurement precision
If a large amount of hardware resources are used to establish the timing model with high accuracy, then the measurement precision is improved, but the device complexity worsens
Solution Approach 1:
The patent extracts and removes unnecessary aggressor paths and high-fanout circuit devices from the timing model that do not significantly impact timing analysis accuracy. By selectively eliminating these components, the analysis complexity is reduced while maintaining the essential timing characteristics, thus achieving faster analysis without sacrificing critical accuracy.
3Productivity
If the timing model complexity is reduced to improve analysis efficiency, then the productivity is improved, but the measurement precision deteriorates
Solution Approach 1:
The patent applies local quality by differentiating between critical and non-critical circuit elements. Victim paths and their immediate aggressors are retained with high fidelity for accurate timing analysis, while distant or less impactful aggressor paths are removed. This localized retention strategy ensures timing accuracy is maintained where it matters most while reducing overall model complexity.
Solution Approach 2:
The patent applies partial action by performing timing analysis only on the most critical paths and circuits rather than analyzing the entire circuit comprehensively. By focusing computational resources on victim paths and their immediate aggressors, the method achieves sufficient timing accuracy for decision-making while dramatically reducing overall analysis time.
Data Source
AI summary
An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.


