Timing Model Building for Gate-Level Netlist Analysis
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Solution Overview
Problem
Current timing models for static timing analysis (STA) in complex circuit designs often include unnecessary cells and fail to adequately consider cross-coupled effects between cells, leading to inefficiencies and inaccurate signal integrity analysis, requiring significant computational resources and time.
Innovation Solution
A timing model building method that generates an interface net and an identified internal net for a gate-level netlist, excluding cells driven by unconstrained clock trees and cross-coupling the internal net with the interface net, to create a concise and accurate timing model for top-level analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional timing models (ETM, ILM, hyperscale model) are used for STA, then the analysis can be performed at block level to reduce hardware resources and time, but the models include excessive non-necessary cells or inadequate necessary cells, leading to inaccurate signal integrity analysis
Solution Approach 1:
The timing model is segmented into two distinct parts: interface nets (containing cells with timing constraints at block boundaries) and internal nets (containing cells driven by unconstrained clock trees). This segmentation allows the model to include only necessary cells for signal integrity analysis while excluding non-necessary cells, thereby improving accuracy without excessive complexity
Solution Approach 2:
Cells driven by unconstrained clock trees are extracted and excluded from the interface net, forming a separate internal net. This extraction removes non-necessary cells from the timing model that would otherwise consume hardware resources and complicate the model, while preserving the accuracy needed for signal integrity analysis
2Reliability
If traditional timing models include all cells for comprehensive coverage, then necessary cells are included, but excessive non-necessary cells increase hardware resources and computation time
Solution Approach 1:
Different parts of the circuit are treated with different levels of detail: interface nets maintain high fidelity with all necessary cells and timing constraints for accurate signal integrity analysis, while internal nets use a simplified representation that excludes non-necessary cells. This local quality differentiation improves computation efficiency while maintaining reliability where needed
Solution Approach 2:
Instead of including all cells (excessive action), the timing model includes only the partial set of cells necessary for accurate signal integrity analysis at the block level. This partial action excludes cells driven by unconstrained clock trees that would not contribute to the accuracy of the top-level STA, thereby improving productivity while maintaining sufficient reliability
3Productivity
If block-level analysis is performed to reduce hardware resources and time, then resource consumption is reduced, but cross-coupled effects between cells are inadequately considered
Solution Approach 1:
The interface net acts as an intermediary that captures the cross-coupled effects between internal nets and the rest of the system. By including cells with timing constraints and their interconnections in the interface net, the model preserves cross-coupled effect information while maintaining block-level analysis efficiency, thus improving measurement precision without sacrificing productivity
Data Source
AI summary
A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.