Structurally-Aware Timing Model for Hierarchical Circuit Design
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Solution Overview
Problem
Current electronic design automation (EDA) systems for integrated circuits face challenges in accurately performing sign-off, pessimism reduction, optimization, and verification of hierarchical system designs due to obscured structural features in timing models, leading to sub-optimal power, performance, and area (PPA) characteristics and prolonged design cycles.
Innovation Solution
A structurally-aware timing model is generated and used to represent the operational timing characteristics of a circuit design, incorporating structural weights associated with timing arcs to reduce pessimism and improve accuracy in timing analysis, while obscuring implementation details to protect intellectual property.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a timing model with obscured structural features is used in hierarchical circuit design, then intellectual property is protected, but timing analysis accuracy deteriorates and pessimism increases
Solution Approach 1:
The patent introduces a timing model as an intermediary representation that sits between the detailed circuit design and the timing analysis process. This timing model contains structured timing information (timing arcs, endpoints, structural weights) that enables accurate timing analysis without exposing the actual implementation details of the circuit design, thus protecting intellectual property while maintaining analysis accuracy
Solution Approach 2:
The patent transforms the circuit design into a timing model by changing the representation parameters from structural implementation details to timing-specific parameters (timing arcs, endpoints, structural weights). This parameter transformation allows timing analysis to be performed on the transformed representation without access to the original structural details, resolving the contradiction between IP protection and analysis accuracy
2Reliability
If pessimism is incorporated in timing analysis to ensure reliability, then timing violations are caught conservatively, but power/performance/area optimization is degraded
Solution Approach 1:
The patent applies local quality by assigning different structural weights to different timing arcs based on their specific structural characteristics (such as number of logic stages, wire length, fan-out). This localized weighting provides more nuanced and accurate timing analysis compared to uniform pessimism, allowing for better optimization while maintaining reliability by being conservative only where structurally justified
3Measurement precision
If detailed structural features are exposed in timing models, then timing analysis accuracy is improved, but intellectual property protection is weakened
Solution Approach 1:
The patent extracts only the timing-relevant structural information from the detailed circuit design to create the timing model. It takes out the essential timing characteristics (timing arcs, endpoints, structural weights) while leaving behind the detailed implementation information that would expose intellectual property. This selective extraction maintains timing analysis accuracy without disclosing sensitive design information
4Measurement precision
If iterative loops are performed for pessimism reduction, then timing analysis accuracy is improved, but design cycle time is prolonged
Solution Approach 1:
The patent performs preliminary action by pre-calculating and embedding structural weights in the timing model during model creation. This preliminary structuring of timing information enables more accurate single-pass timing analysis without requiring multiple iterative loops for pessimism reduction, thus improving timing analysis accuracy while reducing design cycle time
Data Source
AI summary
A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.