Timing Model Reduction via Dominance Adjacency Data Structure
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Solution Overview
Problem
Current timing analyses for electronic circuits require significant runtime due to the large number of timing models needed for complex electronic design components with multiple inputs, leading to inefficient processing and high computational costs.
Innovation Solution
The method involves determining dominance relations among timing models, generating a dominance adjacency data structure, and transforming it into a reduced set of models, which are then used in timing analyses, reducing the number of models through graph condensation and identifying strongly connected components with zero input valency vertices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of timing models are used for complex electronic design components with multiple inputs, then timing analysis accuracy is improved, but runtime and computational resources increase significantly
Solution Approach 1:
The patent extracts and removes redundant timing models from the complete set of timing models. By identifying and eliminating models that do not contribute to timing analysis accuracy, the system reduces the number of models that need to be processed, thereby decreasing runtime while maintaining analysis precision.
Solution Approach 2:
The patent changes the parameter of timing model quantity from a large complete set to a reduced optimized set. Through systematic reduction techniques, the number of timing models is transformed from potentially thousands to a manageable subset, directly addressing the runtime issue while preserving accuracy.
2Reliability
If a large number of timing models are used for complex electronic design components, then comprehensive timing coverage is achieved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential timing models needed for comprehensive timing coverage, removing redundant models from the timing library. This extraction process reduces library complexity while ensuring that all critical timing scenarios are still covered.
Solution Approach 2:
Instead of starting with a complete set of timing models and trying to maintain coverage, the patent inverts the approach by starting with a reduced set and systematically verifying that timing coverage is maintained. This inversion simplifies the timing library structure while ensuring reliability.
3Measurement precision
If timing analysis is performed with complete timing models, then accurate delay calculations are obtained, but computational resources are consumed excessively
Solution Approach 1:
The patent extracts and removes unnecessary timing models from the complete set, reducing the computational workload. By processing only the essential subset of timing models, the system maintains delay calculation accuracy while significantly reducing energy consumption and computational resource usage.
Solution Approach 2:
The patent applies partial action by using only the necessary portion of timing models rather than the complete set. This partial approach is sufficient to achieve accurate delay calculations without the excessive computational resources required by the full model set.
Data Source
AI summary
Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.