Timing Over Packet Demarcation Entity for Clock Synchronization

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Solution Overview

Problem

In packet switched networks, maintaining synchronization of clocks is more difficult and error-prone due to delay asymmetry and packet delay variation, which increases complexity, expense, and bandwidth overhead, making it challenging to meet quality of service standards for cellular networks.

Innovation Solution

The introduction of a Timing Over Packet Demarcation Entity (ToPDE) that monitors synchronization and quality of frequency and time distribution within the network at a low bandwidth cost, using local and copied timestamps to determine frequency and time differences, and generating statistics for network performance evaluation, while optionally disciplining its local clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional clock synchronization methods are used in packet switched networks, then clocks can be synchronized, but the complexity, expense, and bandwidth overhead increase significantly

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidsynchronization system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a transparent clock as an intermediary device that measures packet residence time within the network and inserts this measurement into timing packets. This intermediary approach allows end nodes to calculate synchronization without complex processing at each node, reducing overall system complexity while maintaining accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional mechanical clock synchronization methods with a packet-based timing measurement system. Instead of using physical clock signals and complex synchronization protocols, the system uses packet residence time measurements to derive synchronization information, simplifying the mechanical complexity of traditional approaches.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If traditional clock synchronization methods are used in packet switched networks, then clocks can be synchronized, but bandwidth overhead increases

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidbandwidth overhead
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The transparent clock copies the residence time measurement from the timing packet and inserts it into the packet payload. This copying approach allows the timing information to be transmitted efficiently alongside data packets without requiring separate dedicated timing channels, reducing bandwidth overhead.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The timing packets serve multiple functions: they carry synchronization timing information and simultaneously convey network delay characteristics through the inserted residence time measurement. This multi-functionality reduces the need for separate measurement packets, lowering overall bandwidth overhead.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If fine-granularity sampling is implemented for network monitoring, then monitoring accuracy improves, but bandwidth overhead increases

Engineering Contradiction:
Improvemonitoring accuracyVSAvoidbandwidth overhead
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The transparent clock inserts residence time information selectively into timing packets rather than all packets. This partial action approach provides fine-granularity monitoring accuracy where needed (in timing packets) without the excessive bandwidth overhead of monitoring all network traffic, achieving a balanced compromise.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9525502B2Timing over packet demarcation entity
Publication Date: 2016.12.20 RAD DATA COMMUNICATIONS
  • US9525502B2 patent drawing
  • US9525502B2 patent drawing
  • US9525502B2 patent drawing

AI summary

Apparatus for synchronizing a local clock to a master clock, the apparatus comprising: at least one port for receiving and transmitting packets; a local clock; and a packet inspector that uses time from the local clock to timestamp packets received at a port of the at least one port, copies timing information from the received packets if the packets are timing distribution packets that are transmitted between a master clock and a slave clock in order to synchronize the slave clock to the master clock, and forwards the received packets for transmission from a port of the at least one port towards a packet destination that is not a packet source from where the packets originate, wherein the local clock uses the copied timing information and timestamps to synchronize the local clock to the master clock.