Timing Path Identification in Programmable Integrated Circuits
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Solution Overview
Problem
Conventional analysis tools are unable to identify attribute-sensitive timing paths within circuit blocks of programmable integrated circuits, particularly those that conditionally exist based on component bypasses, leading to a time-consuming and tedious manual analysis process.
Innovation Solution
A computer-implemented method generates a map file from a graphic representation of the circuit block, identifies sub-paths, and selectively combines them based on commonality of starting and ending points to determine timing paths, including dependency conditions and delays, classifying them into setup/hold, combinatorial, clock-to-output, and maximum frequency paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analysis tools are used to identify timing paths, then the analysis process is simple to operate, but the tools cannot identify attribute-sensitive timing paths that conditionally exist based on component bypasses
Solution Approach 1:
The patent segments the timing path identification process into multiple stages: first generating all possible sub-paths from the circuit block diagram, then systematically combining these sub-paths based on attribute conditions to form complete timing paths. This segmentation allows the tool to handle complex attribute-sensitive paths by breaking them down into manageable units that can be processed and combined systematically.
Solution Approach 2:
The patent implements dynamic path generation where the set of timing paths is not fixed but depends on the attribute values of circuit components. The tool dynamically generates timing paths based on the configuration attributes (such as bypass conditions), allowing the same circuit block to produce different timing path sets depending on its operational state. This dynamic approach enables accurate identification of attribute-sensitive timing paths.
2Measurement precision
If manual analysis is performed to identify all timing paths, then complete timing path identification can be achieved, but the process becomes time-consuming and tedious
Solution Approach 1:
The patent enables the analysis tool to perform self-service by automatically generating and combining sub-paths to identify all timing paths without requiring manual intervention. The tool systematically processes the circuit block diagram, generates sub-paths, combines them according to attribute conditions, and produces complete timing path lists automatically. This self-service capability eliminates the time-consuming manual analysis while maintaining complete timing path identification.
Solution Approach 2:
The patent performs preliminary actions by first generating all possible sub-paths from the circuit block diagram before combining them to form complete timing paths. This preliminary generation of sub-paths creates a foundation that can be systematically combined later, avoiding the need for manual analysis of the entire complex path space. The preliminary breakdown into sub-paths makes the subsequent combination process automated and efficient.
3Productivity
If the number of sub-paths is reduced to simplify processing, then the analysis becomes faster, but the completeness of timing path identification is compromised
Solution Approach 1:
The patent segments the timing path identification into two phases: first generating a comprehensive set of sub-paths (which may be numerous), then systematically combining only the necessary sub-paths based on attribute conditions. This segmentation allows the tool to maintain completeness in sub-path generation while achieving speed through selective combination in the second phase, avoiding unnecessary processing of irrelevant paths.
Solution Approach 2:
The patent applies partial action by generating sub-paths that may be more numerous than the final timing paths, but then uses selective combination based on attribute conditions to reduce this set to only the relevant timing paths. This approach ensures completeness in the initial generation phase while achieving efficiency in the final filtering and combination phase, balancing productivity with measurement precision.
Data Source
AI summary
A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.