Integrator-Based Timing Recovery for High-Speed CDR Phase Detection
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Solution Overview
Problem
Conventional clock and data recovery (CDR) modules in high-speed communication links face issues with excessive clock phases, inter-symbol interference (ISI), specific transition patterns, and undetermined threshold voltages, leading to reduced timing and voltage margins.
Innovation Solution
A phase detection technique using an integrator on the timing path to determine the correct clock sampling phase, eliminating the need for additional clock phases, ISI, specific transition patterns, and digital-to-analog converters (DACs), by integrating data samples and adjusting the clock position based on integrated voltage signs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDR modules use multiple clock phases for data sampling, then phase detection capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the phase detection function from the data sampling path by using a separate integrator dedicated to phase detection. This allows the data slicer to use only a single clock phase for sampling, while the integrator independently determines phase error using the same clock signal, thereby reducing the number of clock phases needed without compromising phase detection accuracy.
Solution Approach 2:
The integrator serves as an intermediary component that processes the data signal separately to generate phase detection information. Instead of using multiple clock phases directly, the system introduces an integrator that accumulates the product of the data signal and delayed versions of itself, providing phase error information without requiring multiple sampling clocks.
2Measurement precision
If conventional approaches require inter-symbol interference (ISI) on input data, then transition detection is improved, but adaptability to different data patterns deteriorates
Solution Approach 1:
The integrator performs self-service by using the data signal itself as both input and reference. The phase detection mechanism multiplies the data signal with a delayed version of itself, allowing the signal to detect its own transitions without requiring external test patterns or ISI conditions. This makes the system adaptable to any data pattern while maintaining precise transition detection.
3Reliability
If conventional CDR modules use DACs for threshold voltage adjustment, then voltage margin optimization is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent replaces expensive and complex DAC components with a simple integrator-based threshold generation mechanism. The integrator naturally produces a zero-crossing threshold voltage without requiring digital-to-analog conversion circuitry, significantly simplifying the manufacturing process while maintaining optimal voltage margins for reliable data sampling.
Solution Approach 2:
The patent substitutes the mechanical/electrical DAC system with a signal processing approach using integration. Instead of using a DAC to generate and adjust threshold voltages, the system uses the integrator's output to naturally establish the threshold, replacing a complex hardware subsystem with a simpler computational function.
4Measurement precision
If conventional approaches require specific transition patterns, then phase detection accuracy is improved, but ease of operation deteriorates
Solution Approach 1:
The phase detection mechanism uses the data signal itself to generate the necessary transition information through self-multiplication with a delayed version. This eliminates the need for external test patterns or specific data sequences, allowing the system to operate continuously on normal data traffic without requiring specialized operational modes or pattern generation circuitry.
Data Source
AI summary
A method and an apparatus are provided in which at least one data slicer of a receiver samples a signal based on a clock sampling position to obtain a first data sample and a second data sample. An integrator of the receiver integrates the signal from the first data sample to the second data sample to generate an integrated voltage. A first data slicer of the receiver samples the integrated voltage at a time of the second data sample to obtain an integrated sample. A phase detector of the receiver determines whether the clock sampling position requires adjustment based on a sign of the integrated sample.