Universal Timing Recovery Circuit for Modulation Compatibility
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Solution Overview
Problem
Existing timing recovery circuits in receivers are unable to provide Fs/4 down-conversion for both continuous phase modulation and linear stream modulation signals, leading to inter-symbol interference and potential data loss due to discrepancies between the sample clocks at the transmitter and receiver.
Innovation Solution
A digital timing recovery circuit that performs Fs/4 down-conversion and filtering prior to the squaring non-linearity process, allowing for timing recovery of both continuous phase modulated and linear stream modulated signals by generating in-phase and quadrature phase components, and using a square-law non-linearity processor to accentuate timing information, followed by low-pass filtering and frequency de-rotation to provide accurate timing estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional timing recovery architecture is used for linear stream modulation, then timing recovery can be achieved, but the circuit cannot provide Fs/4 down-conversion for both continuous phase modulation and linear stream modulation signals
Solution Approach 1:
The patent implements a universal timing recovery circuit that can handle both continuous phase modulation and linear stream modulation signals using a single integrated architecture. The circuit employs a unified signal processing path that performs Fs/4 down-conversion and filtering operations common to both modulation types, eliminating the need for separate timing recovery paths for each modulation scheme.
Solution Approach 2:
The patent applies preliminary Fs/4 down-conversion and filtering operations before the squaring non-linearity process. This preliminary action prepares the signal in advance, converting it to an intermediate frequency where timing information can be extracted more effectively. By performing this preparation step beforehand, the circuit achieves better timing recovery performance for both modulation types without increasing overall complexity.
2Measurement precision
If signal down-conversion and filtering is performed prior to squaring non-linearity, then timing recovery accuracy improves, but processing time increases
Solution Approach 1:
The patent performs Fs/4 down-conversion and filtering as preliminary actions before the squaring non-linearity process. This preparation step transforms the signal into an intermediate frequency representation that enhances timing information visibility. Although this adds processing steps, the efficient implementation of these preliminary operations enables accurate timing recovery without excessive time penalty.
3Productivity
If the circuit operates at high data rates, then productivity increases, but noise and processing complexity increase
Solution Approach 1:
The patent applies preliminary Fs/4 down-conversion and filtering operations before non-linearity processing. This preliminary action reduces the signal frequency to an intermediate level where timing information can be extracted more efficiently. By performing this frequency transformation in advance, the circuit can operate at high data rates while maintaining manageable processing complexity, as the heavy computational tasks are performed on lower-frequency signals.
Solution Approach 2:
The patent changes the frequency parameter of the signal through Fs/4 down-conversion, transforming it from a high-frequency carrier to a lower intermediate frequency. This parameter change enables the subsequent non-linearity processing to operate more efficiently at reduced frequencies, allowing the circuit to maintain high productivity data rates while reducing the actual processing complexity of the timing recovery operations.
Data Source
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AI summary
A timing recovery system that provides a timing estimate between a transmitter clock and a receiver clock. The system includes a down-converter that converts a received intermediate frequency signal in the receiver and down-converts, using Fs/4 down-conversion, the received signal into baseband in-phase and quadrature phase signals. The baseband in-phase and quadrature phase signals are sent to a direct down-converter that frequency shifts the in-phase and quadrature phase. The frequency-shifted in-phase and quadrature phase baseband signals are then low-pass filtered in order to isolate the frequency components of interest, reduce noise, and remove zeros that are artifacts of the Fs/4 down-conversion. The signals are sent to a square-law non-linearity circuit that provides squaring non-linearity to generate non-linear in-phase and quadrature phase signals. The non-linear in-phase and quadrature phase signals are sent to a single-pole, low-pass post-filter circuit that generates the timing estimate.