Supplementary Timing Recovery Circuit for Signal Processing
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Solution Overview
Problem
Timing recovery techniques in electrical devices, such as communication and storage devices, face challenges in accurately reconstructing digital data from analog signals due to timing errors, which can result in data reconstruction with either fast response or high accuracy but not both simultaneously.
Innovation Solution
A signal processing circuit comprising an analog to digital converter, an equalizer, a first timing compensation module, and a second timing compensation module, which detect and correct timing errors using zero-crossing detection and phase-shifting, allowing for both fast response and high accuracy in data reconstruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single timing recovery circuit is used, then the device complexity is reduced, but the measurement precision of timing errors deteriorates
Solution Approach 1:
The timing recovery function is divided into two separate circuits: a first timing recovery circuit that operates on the original digital signal to provide fast response, and a second timing recovery circuit that operates on the equalized digital signal to provide high accuracy. This segmentation allows each circuit to be optimized for its specific function without compromise.
Solution Approach 2:
The patent introduces a new dimension by applying timing recovery at two different stages of signal processing: before equalization (first timing recovery) and after equalization (second timing recovery). This multi-stage approach in the signal processing dimension enables both fast response and high accuracy to be achieved simultaneously.
2Speed
If timing recovery is performed before equalization, then the response speed is improved, but the timing error detection accuracy deteriorates due to signal distortion
Solution Approach 1:
The timing recovery process is segmented into two distinct stages: first timing recovery on the original signal for fast response, and second timing recovery on the equalized signal for high accuracy. This segmentation resolves the contradiction by assigning different functions to different stages.
Solution Approach 2:
The first timing recovery circuit performs preliminary timing correction on the original digital signal before equalization, providing fast initial alignment. This preliminary action prepares the signal for subsequent high-precision equalization and second timing recovery.
3Measurement precision
If timing recovery is performed after equalization, then the timing error detection accuracy is improved, but the response speed deteriorates due to additional processing delay
Solution Approach 1:
The timing recovery function is segmented into two circuits operating at different stages: the first timing recovery circuit provides fast initial response on the original signal, while the second timing recovery circuit provides high accuracy on the equalized signal. This segmentation eliminates the trade-off by distributing functions across stages.
Solution Approach 2:
The patent maintains continuous timing recovery action throughout the signal processing chain, with the first timing recovery circuit continuously adjusting timing on the original signal and the second timing recovery circuit continuously refining timing on the equalized signal. This continuous multi-stage action ensures both speed and accuracy.
Data Source
AI summary
Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes an analog to digital converter (ADC) configured to receive an analog input signal, sample the analog input signal based on a sampling clock signal, and convert the sampled analog input signal into a digital output signal, an equalizer configured to equalize the digital output signal, a phase-shift module configured to phase-shift the equalized digital output signal based on a phase-shift signal, and a timing compensation module coupled to the phase-shift module to detect a timing error, and to adjust the phase-shift signal based on the timing error.