Timing Recovery Circuit Using Equalizer Coefficients for Stable Sampling
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Solution Overview
Problem
In high-speed data communication systems, such as DSL, inter-symbol interference (ISI) caused by channel distortion leads to timing errors and reduced communication reliability, with existing timing recovery methods like the M&M algorithm requiring symmetric input signals and substantial hardware for precise control, and converging properties of Decision Feedback Equalizers (DFE) being unstable due to initial phase issues.
Innovation Solution
A timing recovery circuit that includes a timing error detector generating a control voltage signal based on differences between feed-forward and feedback filter coefficients, with a loop filter and voltage-controlled oscillator to stabilize the sampling clock, and a method that revises timing errors by calculating differences between initial and converging coefficient values to achieve symmetric channel impulse response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the M&M algorithm is used for timing recovery, then timing information can be extracted from received data, but the method requires symmetric input signals and substantial hardware resources
Solution Approach 1:
The patent extracts timing information by calculating the difference between feed-forward filter coefficients and feedback filter coefficients, rather than using the complex M&M algorithm. This coefficient difference approach yields timing recovery results comparable to the M&M algorithm while requiring substantially less hardware resources and not requiring symmetric input signals.
Solution Approach 2:
The patent uses a simplified copying approach where timing information is derived by copying and comparing coefficient values from the equalizer filters rather than performing complex cross-correlation operations. This coefficient-based copying method reduces computational complexity while maintaining timing recovery accuracy.
2Measurement precision
If the M&M algorithm is used for timing recovery, then timing information can be extracted, but the converging properties are unstable due to initial phase issues
Solution Approach 1:
The patent applies preliminary action by using initial coefficient values from the equalizer to generate timing errors before the full M&M algorithm converges. By calculating timing information based on coefficient differences from the start, the system achieves stable convergence without being affected by initial phase issues that plague the traditional M&M algorithm.
Solution Approach 2:
The patent implements feedback by continuously using the generated timing errors to adjust the sampling clock through the loop filter and voltage-controlled oscillator. This feedback mechanism stabilizes the converging properties by continuously correcting timing deviations based on the coefficient differences, ensuring robust convergence regardless of initial phase conditions.
3Reliability
If channel distortion is present in high-speed data communication systems, then inter-symbol interference occurs, but existing methods cannot effectively compensate without increasing power or bandwidth
Solution Approach 1:
The patent applies self-service by using the received signal's own coefficient information from the equalizer filters to generate timing errors and compensate for channel distortion. The system leverages the existing equalizer coefficients to create timing recovery without requiring additional external references or increasing transmit power, achieving ISI compensation through self-generated timing information.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces timing errors and stabilizes the sampling clock, improving communication reliability by converging to a minimum timing error and maintaining symmetric channel impulse response, thus enhancing the reliability of high-speed data communication systems.
Implementation Method 1
a voltage controlled oscillator generating a sampling clock for the receiver based on the generated control voltage signal
Data Source
AI summary
A timing recovery circuit for a receiver may include a timing error detector that generates a timing error based on differences between coefficients of a feed-forward filter and a feed-back filter. The timing recovery circuit may include a loop filter which generates a control voltage signal based on the timing error, and a voltage controlled oscillator that generates a sampling clock for the receiver based on the generated control voltage signal.