Timing Signal Adjustment Circuit for Memory Data Capture
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Solution Overview
Problem
In fully synchronous memory systems, the read data path often fails to meet the setup time requirements for capturing data in the memory controller circuit due to the lack of a timing signal during read operations, limiting data transmission rates.
Innovation Solution
An integrated circuit with a timing signal adjustment circuit that delays the read timing signal to ensure the setup time is met, allowing for higher data transmission rates by generating a second timing signal based on the first timing signal and buffering it for external transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If no timing signal is transmitted during read operations in a fully synchronous memory system, then the system operates in fully synchronous mode, but the read data path fails to meet setup time requirements for capturing data
Solution Approach 1:
The patent segments the timing signal path into two separate paths: one path transmits the timing signal along with data during write operations, and another path generates a local timing signal for read operations. This segmentation allows independent optimization of each path, enabling the read path to meet setup time requirements while maintaining fully synchronous operation.
Solution Approach 2:
The patent applies preliminary action by generating and buffering the timing signal in advance before data arrival during read operations. The timing signal is prepared ahead of time and held in a buffer, ensuring it is ready and stable when data needs to be captured, thus meeting setup time requirements without limiting data transmission rate.
2Reliability
If a timing signal is transmitted during read operations, then setup time requirements can be met, but the system complexity increases due to requiring phase-locked loop or delay-locked loop circuits
Solution Approach 1:
The patent extracts the timing signal transmission requirement from the data path by generating a separate local timing signal specifically for read operations. This extraction eliminates the need for complex phase-locked loop or delay-locked loop circuits that would be required to synchronize external timing signals, thereby reducing device complexity while still meeting setup time requirements.
Solution Approach 2:
The patent creates a local copy of the timing signal function by generating a timing signal within the memory controller circuit that mirrors the functionality of an external timing signal. This copying approach avoids the complexity of transmitting and synchronizing actual external timing signals during read operations, simplifying the overall system architecture.
3Reliability
If the timing signal is delayed to meet setup time, then data capture reliability improves, but the timing signal transmission time increases
Solution Approach 1:
The patent applies preliminary action by generating and buffering the timing signal in advance before data arrival. The timing signal is prepared ahead of time and held ready in a buffer, eliminating the need for real-time delays during data capture. This approach ensures reliable data capture without adding transmission time delays.
Solution Approach 2:
The patent introduces a buffer circuit as an intermediary between the timing signal generator and the data capture circuitry. This buffer mediates the timing relationship by holding the timing signal ready for immediate use, ensuring setup time requirements are met without requiring additional delay elements that would increase transmission time.
Data Source
AI summary
An integrated circuit includes a delay circuit, a buffer circuit, and a storage circuit. The delay circuit delays a first timing signal to generate a second timing signal. The buffer circuit generates a third timing signal for transmission to an external device. The third timing signal is generated based on the first timing signal. The external device provides data to the integrated circuit based on the third timing signal. The storage circuit captures the data transmitted from the external device in response to the second timing signal.