Delayed Timing Signal Calibration for Processor-Memory Data Links
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Solution Overview
Problem
Current electronic circuits face challenges in accurately synchronizing timing signals between processor and memory integrated circuits during data transmission, leading to inefficiencies in write and read operations due to variations in delays caused by temperature, supply voltage, and process variations.
Innovation Solution
The implementation of a system where the processor integrated circuit delays internal timing signals and adjusts external timing signals to match these delays, using calibration modes to ensure precise synchronization through buffer circuits and replica circuits, reducing the need for additional replica circuits in the memory integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replica circuits are implemented in the memory integrated circuit to delay write data signals, then timing synchronization is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the timing delay function from the memory integrated circuit and relocates it to the processor integrated circuit. The processor now generates delayed timing signals that account for buffer delays, eliminating the need for replica circuits in the memory device. This reduces memory device complexity while maintaining timing synchronization.
Solution Approach 2:
The patent introduces buffer circuits as intermediaries between the memory device and processor. These buffers are calibrated to provide specific delays, and the processor compensates for these delays by adjusting its timing signals. This intermediary approach enables precise timing control without requiring complex replica circuits in the memory device.
2Measurement precision
If multiple replica circuits are used in the memory integrated circuit for timing delay, then data capture accuracy improves, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming replica circuits from the memory integrated circuit and consolidates the timing delay function in the processor integrated circuit. The processor generates pre-delayed timing signals that compensate for buffer delays, achieving accurate data capture without the continuous power consumption of replica circuits in the memory device.
Solution Approach 2:
The patent applies preliminary action by having the processor integrate circuit advance-delay its timing signals before transmission to the memory device. This pre-delay compensates for the known buffer delays, ensuring that timing signals arrive at the correct moment without requiring active replica circuits in the memory device during operation.
3Productivity
If timing signals are transmitted with data during read operations, then data transmission efficiency improves, but timing synchronization becomes more difficult due to variations
Solution Approach 1:
The patent applies preliminary action by having the processor integrated circuit pre-calculate and apply delay compensation to timing signals before transmission. The processor accounts for buffer delays and generates timing signals that are already adjusted, ensuring accurate synchronization upon arrival at the memory device even as temperature and voltage vary.
Solution Approach 2:
The patent implements calibration modes that provide feedback mechanisms to determine optimal buffer delays under different operating conditions. During calibration, the system measures actual buffer delays and adjusts timing signal delays accordingly, enabling the processor to compensate for variations in temperature, voltage, and process conditions while maintaining synchronous operation.
Data Source
AI summary
An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.