Delayed Timing Signal Calibration for Source-Synchronous Data Transfer
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Solution Overview
Problem
In computing systems, the synchronization of timing signals between processor and memory integrated circuits is challenging due to variations in delays, leading to inefficiencies in data transmission during write and read operations, particularly in source synchronous systems where precise timing is crucial for data capture and storage.
Innovation Solution
The implementation of a system where the processor integrated circuit delays internal timing signals to match external delays in the memory integrated circuit, using calibration modes to adjust and synchronize these delays, thereby ensuring that data is captured accurately and efficiently during both write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replica circuits are used in receiving circuits to delay data signals, then timing synchronization is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the timing delay function from the receiving circuits (where replica circuits would traditionally be needed) and relocates it to the transmitting circuits. The transmitting circuits now include delay circuits that delay data signals before transmission, eliminating the need for replica circuits in the receiving circuits while maintaining timing synchronization.
Solution Approach 2:
Instead of having receiving circuits delay data signals using replica circuits (the traditional approach), the patent inverts the approach by having transmitting circuits delay the data signals before transmission. This reversal eliminates the need for complex replica circuits in the receiving end.
2Measurement precision
If replica circuits are implemented in receiving circuits, then data capture accuracy is maintained, but power consumption increases
Solution Approach 1:
The timing delay functionality is extracted from the power-consuming replica circuits in receiving circuits and relocated to the transmitting circuits. This eliminates the need for replica circuits in receiving circuits while maintaining data capture accuracy, thereby reducing power consumption.
3Speed
If timing signals are transmitted without delay adjustment, then transmission speed is maintained, but synchronization accuracy deteriorates due to delay variations
Solution Approach 1:
The patent applies preliminary action by delaying data signals in the transmitting circuits before transmission. The delay circuits in the transmitting circuits pre-adjust the timing of data signals to compensate for expected delays in the transmission path, ensuring synchronization accuracy is maintained without requiring additional delay adjustment in the receiving circuits.
Solution Approach 2:
The patent implements feedback through calibration modes where timing relationships are measured and adjusted. The system includes calibration circuits that determine optimal delay values by analyzing timing relationships between transmitted and received signals, then use this feedback to adjust the delay circuits in transmitting circuits for optimal synchronization.
Data Source
AI summary
An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.