Timing Signal Regeneration in Master-Slave Loop Networks

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Solution Overview

Problem

Existing methods for regenerating a timing signal in digital data communication using a master/slave loop timing mode struggle to accurately adjust the frequency of the timing signal due to variable data transmission delays and network interference, leading to incorrect frequency adjustments and potential differences between the regenerated and original timing signal frequencies.

Innovation Solution

The method involves forming indicators in both the master and slave network elements based on buffer memory fullness and time stamps to assess frequency deviations, with the slave adjusting its timing signal frequency using a combined control value from these indicators to minimize incorrect adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the slave network element adjusts the timing signal frequency based on buffer memory fullness, then the frequency deviation between master and slave timing signals is reduced, but network interference and variable transmission delays cause incorrect frequency adjustments

Engineering Contradiction:
Improvefrequency deviation measurement accuracyVSAvoidfrequency adjustment reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the slave network element continuously monitors buffer memory fullness and uses this information to adjust the timing signal frequency. The feedback loop compares the actual frequency deviation with the desired deviation and dynamically adjusts the timing signal to minimize errors, thereby improving measurement precision while maintaining adjustment reliability despite network interference

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The buffer memory fullness serves as an intermediary indicator that indirectly reflects frequency deviations between master and slave timing signals. Instead of directly measuring frequency deviation which is susceptible to network interference, the system uses buffer fullness as a mediator that provides more reliable adjustment information by smoothing out the effects of variable transmission delays

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the system uses buffer memory fullness as an indicator for frequency adjustment, then the adjustment responds to actual data flow conditions, but transmission delays and network interference cause incorrect interpretation of the indicator

Engineering Contradiction:
Improveadaptation to data flow conditionsVSAvoidfrequency deviation indication accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The system uses feedback control to continuously monitor buffer memory fullness and adjust the timing signal frequency accordingly. The feedback mechanism distinguishes between legitimate frequency deviations (indicating actual data flow conditions) and false indications (caused by transmission delays), thereby maintaining adaptability while improving measurement precision through dynamic error correction

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The buffer memory acts as a preliminary processing stage that smooths out the effects of variable transmission delays before the frequency adjustment decision is made. By anticipating and compensating for delay variations in advance, the system can more accurately interpret buffer fullness as an indicator of actual frequency deviations rather than transient delay effects

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP1867082B1Method and arrangement for regenerating a timing signal in digital data communication
Publication Date: 2014.01.22 TELLABS
  • EP1867082B1 patent drawingFigure 1
  • EP1867082B1 patent drawingFigure 2
  • EP1867082B1 patent drawingFigure 3

AI summary

The invention relates to a method and arrangement for regenerating a timing signal in digital data communication, when two network elements (VE301 and VE302) of the data communication network operate in a master/slave loop timing mode. In this operating mode, a data stream (D303) is received in the slave device, the speed of arrival of the part being examined (D301) depending on the reference timing signal (CLK301) present in the master device, and a data stream (U302) is received in the master device, the speed of arrival of the part being examined (U301) depending on the regenerated timing signal (CLK302) present in the slave device. In the method and arrangement according to the invention, two different frequency difference indicators (V301, V302) are formed, and the values or the changes of the values of both of them in relation to time indicate the frequency difference between the reference timing signal and the regenerated timing signal. One frequency difference indicator is formed on the basis of reception taking place in the master device, and the other one on the basis of reception taking place in the slave device. The frequency of the regenerated timing signal is adjusted utilizing the information contained by both frequency difference indicators. The probability of incorrect frequency adjustment measures can be thereby reduced.