Design-Specific Timing Specification for Programmable ICs
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Solution Overview
Problem
Conventional timing specifications for programmable integrated circuits do not accurately account for variations in manufacturing processes, leading to pessimistic performance guarantees and increased costs due to unnecessary headroom for random variations, which can result in underutilization of device capabilities.
Innovation Solution
A method to determine design-specific timing specifications by adjusting delays in different regions of a circuit design to maintain a target timing yield, allowing for better performance guarantees while reducing unnecessary headroom, by using a programmed processor to analyze and optimize timing parameters across various regions of a target device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional timing specifications use average delay measurements de-rated for random variations, then timing yield is guaranteed, but resource delay specifications become pessimistic and device capabilities are underutilized
Solution Approach 1:
The patent applies local quality by differentiating between systematic variations (spatially correlated across the die) and random variations (independent at each location). Instead of applying a uniform de-rating to all resources, the method applies location-specific de-rating factors based on the measured variation characteristics at each die location. This allows resources in different regions to have optimized delay specifications that reflect their actual performance capabilities rather than a conservative worst-case value.
Solution Approach 2:
The patent changes the timing specification parameters by introducing location-dependent de-rating factors that modify the average delay measurements. Rather than using a single de-rated value for all resources, the method adjusts the delay specifications based on the measured random variation magnitude at each specific die location, thereby transforming the timing specification from a uniform conservative value to a set of location-optimized values.
2Reliability
If timing specifications include headroom above average performance, then timing yield is maintained, but performance guarantees are degraded and costs increase
Solution Approach 1:
The patent applies local quality by determining location-specific de-rating factors based on measured random variations at each die location. Resources in regions with lower random variation receive smaller de-rating adjustments, allowing tighter (more optimistic) timing specifications. This localized approach eliminates the need for uniform headroom across all resources, enabling better performance guarantees while maintaining the required timing yield.
Solution Approach 2:
The patent applies partial de-rating rather than excessive de-rating by using measured random variation data to determine appropriate adjustment amounts. Instead of applying a large uniform headroom to all resources, the method applies partial adjustments only where necessary based on actual measured variations, thereby minimizing the impact on performance guarantees while still ensuring timing yield requirements are met.
3Manufacturing precision
If timing specifications are optimized for specific designs, then performance guarantees improve, but specification complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the die into multiple locations or regions and determining separate de-rating factors for each location based on local variation measurements. This segmentation allows the timing specification to be broken down into location-specific values that can be more precisely optimized for each region's characteristics, improving overall specification precision while maintaining a manageable structure through systematic organization.
Solution Approach 2:
The patent applies preliminary action by pre-characterizing the random variation at each die location during manufacturing and storing these measurements. This preliminary characterization data is then used to determine location-specific de-rating factors for timing specifications, eliminating the need for complex real-time calculations during design verification and simplifying the overall specification process.
Data Source
AI summary
A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and second regions of the target device. A circuit design is placed and routed. With a programmed processor, the timing delay of the first timing specification is increased for one or more elements implementing the circuit design in the first region to produce a second timing specification, and a second timing yield of target device is determined from the second timing specification. In response to the second timing yield being larger than a target timing yield, the programmed processor decreases the timing delay of the second timing specification for one or more elements in the second region to compensate for a difference between the second timing yield and the target timing yield to produce a design-specific timing specification.