Unified Timing Verification Tool for IC Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit design tools face challenges in performing unified static timing analysis and dynamic simulation, particularly for both full-custom and ASIC designs, and struggle with issues like false paths, crosstalk, and correlation between aggressors and victims, leading to inefficient delay calculation and maximum operating frequency determination.
Innovation Solution
A timing verification tool that integrates static timing analysis and dynamic simulation into a single environment, capable of handling full-custom and ASIC designs, with features such as automatic circuit structure identification, path search for multi-phase circuits, filtering of false paths, and crosstalk analysis using admittance matrices and voltage transfer in the frequency domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate tools are used for static timing analysis and timing simulation, then each tool can be optimized for its specific function, but the overall verification process becomes complex and requires multiple tools
Solution Approach 1:
The patent combines static timing analysis and timing simulation into a single unified tool environment. The delay calculator integrates both static timing analysis capabilities and dynamic simulation capabilities, allowing users to perform both types of verification without switching between separate tools, thereby reducing toolchain complexity while maintaining verification accuracy
Solution Approach 2:
The unified tool is designed to handle multiple verification functions including static timing analysis, dynamic simulation, false path detection, and crosstalk analysis within a single environment. The delay calculator can operate in different modes (static analysis mode and dynamic simulation mode) to provide universal timing verification capabilities
2Productivity
If conventional static timing analysis tools are used for ASIC designs, then timing verification can be performed efficiently, but they cannot be used for full-custom designs at transistor level
Solution Approach 1:
The delay calculator is designed to handle both gate-level ASIC designs and transistor-level full-custom designs within the same tool environment. It automatically adapts its analysis methods based on the design level, providing efficient timing verification for ASIC designs while also supporting detailed transistor-level analysis for full-custom designs
Solution Approach 2:
The tool changes its internal parameters and analysis depth based on the input design type. For gate-level designs, it uses standard cell library information for efficient analysis, while for transistor-level designs, it performs detailed transistor-level timing analysis, thus adapting to different design complexities
3Reliability
If false paths are not filtered out, then all paths are analyzed comprehensively, but the maximum operating frequency determination becomes meaningless
Solution Approach 1:
The patent implements false path detection and filtering functionality that identifies and extracts false paths from the complete set of circuit paths. By removing false paths before maximum operating frequency calculation, the tool ensures that frequency determination is based only on valid signal paths, thereby maintaining analysis completeness while improving frequency measurement accuracy
4Productivity
If crosstalk effects are not considered, then timing analysis is simpler and faster, but the delay calculation becomes inaccurate
Solution Approach 1:
The tool performs preliminary identification of potential crosstalk victim nets and aggressor nets before conducting full timing analysis. By pre-processing the circuit to identify crosstalk-prone interconnects, the tool can then apply crosstalk analysis only where necessary, maintaining analysis speed while improving delay calculation accuracy for critical paths
Data Source
AI summary
A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out false path and identifying gate with simultaneously changing inputs, (f) Finding maximum operating frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.